Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2007-04-24
2007-04-24
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S126000, C438S612000, C257SE23020, C257SE23021, C257SE23023
Reexamination Certificate
active
10547173
ABSTRACT:
A layer of electrically insulating material is applied to a substrate and a component located thereon, in such a way that said layer follows the surface contours.
REFERENCES:
patent: 5291066 (1994-03-01), Neugebauer et al.
patent: 5616886 (1997-04-01), Romero et al.
patent: 5637922 (1997-06-01), Fillion et al.
patent: 5760418 (1998-06-01), Lee et al.
patent: 6002163 (1999-12-01), Wojnarowski
patent: 2003/0006493 (2003-01-01), Shimoishizaka et al.
patent: 2004/0099940 (2004-05-01), Standing
patent: 2005/0032347 (2005-02-01), Hase et al.
patent: 91 09 295 (1991-11-01), None
patent: 42 28 274 (1994-03-01), None
patent: 199 54 941 (2001-06-01), None
patent: 0 987 760 (2000-03-01), None
patent: WO 01/37338 (2001-05-01), None
patent: WO 03/030247 (2003-04-01), None
Paavo Jalonen; “A new concept® for making fine line substrate for active component in polymer”; Microelectronics Journal; Feb. 2003; pp. 99-107; vol. 34, No. 2; Mackintosh Publications Ltd.; Luton, Germany.
A. Ostmann, A. Neumann, J. Auersperg, C. Ghahremani, G. Sommer, R. Aschenbrenner and H. Reichl; “Integration of Passive and Active Components into Build-Up Layers”; Electronics Packaging Technology Conference 4TH; IEEE 2002; pp. 223-228.
A. Ostmann, A Neumann; “Chip in Polymer—the Next Step in Miniaturization”; Advancing Microelectronics; May/Jun. 2002; pp. 13-15; vol. 29, No. 3.
Burhan Ozmat , Charlie S. Korman, Ray Fillion; “An Advanced Approach to Power Module Packaging”; pp. 8-11; IEEE 2000; 0-7803-6437-6.
R. Fisher, R. Fillion, J. Burgess, and W. Hennessy; “High Frequency, Low Cost, Power Packaging Using Thin Film Power Overlay Technology”; Applied Power Electronics Conference and Exposition, Conference Proceedings Mar. 5-9, 1995; Tenth Annual, Dallas TX, USA; IEEE 1995; pp. 12-17.
Seliger Norbert
Weidner Karl
Zapf Jörg
Brewster William M.
Siemens Aktiengesellschaft
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