Connecting a plurality of peripherals

Details Connecting a plurality of peripherals Connecting a plurality of peripherals

2008-09-02

2011-12-20

Spittle, Matthew (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S317000, C370S351000, C370S357000, C370S363000, C370S387000, C370S388000, C370S395310, C370S541000

Reexamination Certificate

active

08082381

ABSTRACT:
In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

REFERENCES:
patent: 4000487 (1976-12-01), Patterson et al.
patent: 4100601 (1978-07-01), Kaufman et al.
patent: 4553224 (1985-11-01), Struger et al.
patent: 4628446 (1986-12-01), Hoffner, II
patent: 5293489 (1994-03-01), Furui et al.
patent: 5347637 (1994-09-01), Halford
patent: 5508909 (1996-04-01), Maxwell et al.
patent: 5819058 (1998-10-01), Miller et al.
patent: 6233641 (2001-05-01), Graham et al.
patent: 6381664 (2002-04-01), Nishtala et al.
patent: 6499077 (2002-12-01), Abramson et al.
patent: 6553446 (2003-04-01), Miller
patent: 6658559 (2003-12-01), Arora et al.
patent: 6678784 (2004-01-01), Marmash
patent: 6715023 (2004-03-01), Abu-Lebdeh et al.
patent: 6721813 (2004-04-01), Owen et al.
patent: 6732210 (2004-05-01), Mathieson
patent: 6847365 (2005-01-01), Miller et al.
patent: 7332929 (2008-02-01), Normoyle et al.
patent: 7380092 (2008-05-01), Perego et al.
patent: 7487327 (2009-02-01), Chang et al.
patent: 7624222 (2009-11-01), Nanda et al.
patent: 7752413 (2010-07-01), Hoover et al.
patent: 2002/0156943 (2002-10-01), Ishimura et al.
patent: 2003/0131164 (2003-07-01), Abramson et al.
patent: 2006/0059289 (2006-03-01), Ng et al.
patent: 2008/0282102 (2008-11-01), Reddy et al.
patent: 2010/0057974 (2010-03-01), Reddy et al.
patent: 2010/0153618 (2010-06-01), Mathieson et al.
Bluethgen. BEE Mux-Demux Implementation for Connecting Subsystems on 2 FPGAs. Jul. 15, 2002.
Micro Computer Control. IP-201 I2C Bus Multiplexer Board. User's Guide. Revision 1. Jun. 2000.
Erdahl. An Open Architecture for Multiplexing and Processing Telemetry Data. Veda Systems Incorporated. Jul. 15, 1997.
Stok, L. Interconnect Optimisation During Data Path Allocation. IEEE. 1990.
Digital Equipment Corporation. DH11 asynchronous 16-line multiplexer. Maintenance Manual. Apr. 1975.
Campbell Scientific, Inc. AM16/32B Relay Multiplexer. Instruction Manual. Oct. 2009.
Jiang et al. A Multiplexer Controlled by Fuzzy Associate Memory Leaky Bucket in ATM Networks. 1997 IEEE International Symposium on Circuits and Systems. IEEE. Jun. 12, 1997.
Xilinx. Using Dedicated Multiplexers in Spartan-3 Generation FPGAs. Application Note. May 20, 2005.
Non-Final Office Action Date Mailed Sep. 29, 2010; U.S. Appl. No. 12/275,217.
Interview Summary Date Mailed Sep. 30, 2010; U.S. Appl. No. 12/275,217.
Notice of Allowance Date Mailed Jan. 21, 2011; U.S. Appl. No. 12/275,217.
Notice of Allowance Date Mailed Jun. 9, 2011; U.S. Appl. No. 12/275,217.

Affiliated with

Also associated with

Rating

Connecting a plurality of peripherals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Connecting a plurality of peripherals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Connecting a plurality of peripherals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4314030