Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-26
2004-07-20
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S384000
Reexamination Certificate
active
06765269
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnect structures in a semiconductor device. More specifically, the present invention relates to an interconnect strap located over a spacer of a semiconductor structure.
RELATED ART
FIGS. 1A-1D
are cross sectional views illustrating the fabrication of a conventional interconnect strap. As illustrated in
FIG. 1A
, gate oxide
102
, gate electrodes
103
-
104
, and silicon nitride spacers
105
-
108
are formed over substrate
101
. Lightly doped regions
109
-
110
and dielectric
111
are formed in substrate
101
. As illustrated in
FIG. 1B
, photoresist layer
112
is coated, exposed and developed, such that an opening
113
is formed through photoresist layer
112
, exposing spacer
106
. An etch step is then performed, thereby removing spacer
106
through opening
113
. As illustrated in
FIG. 1C
, photoresist layer
112
is stripped, and source/drain implant steps are performed, thereby forming source/drain regions
114
-
115
. As illustrated in
FIG. 1D
, self-aligned CoSi
2
is formed on source/drain regions
114
-
115
and gate electrodes
103
-
104
using high temperature sputtering and in-situ vacuum annealing. Gate electrode
103
and source/drain region
114
are connected by CoSi
2
strap
116
, which is formed where spacer
106
was removed.
Disadvantages associated with the process of
FIGS. 1A-1D
are as follows. First, additional processing is required to selectively and completely remove spacer
106
. This additional processing may present challenges depending on the composition of the spacer material and the intermediate film between spacer
106
and substrate
101
, especially since photoresist layer
112
must remain in place during the removal process. Incomplete removal of spacer
106
will result in failure to form continuous CoSi
2
strap
116
, because CoSi
2
will not form over remaining portions of spacer
106
(i.e., silicon nitride).
In addition, increased junction leakage will result underneath CoSi
2
strap
116
because the source/drain implant must be performed after spacer
106
is selectively removed and before the CoSi
2
is deposited. As a result, source/drain region
114
fully overlaps the lightly doped region
109
under gate electrode
103
, thereby resulting in a shallow and abrupt diode junction underneath CoSi
2
strap
116
.
Furthermore, CoSi2 must be formed on a vertical sidewall of gate electrode
103
. Inadequate cobalt deposition step coverage will result in failure to form a continuous CoSi
2
strap
116
.
It would therefore be desirable to have a silicide strap that couples a gate electrode to a source/drain region, while overcoming the above-described shortcomings of the prior art.
SUMMARY
Accordingly, the present invention provides a method for forming a low-resistance local interconnect structure over an insulator such as a sidewall spacer dielectric. In one embodiment, the method involves fabricating a low-resistance surface strap having a relatively small area between a MOSFET polysilicon gate area and an adjacent source/drain silicon area.
A semiconductor structure is provided that includes a gate, a dielectric spacer located adjacent to a sidewall of the gate, a source/drain region, and a continuous silicide strap located over the gate, the dielectric spacer and the source/drain region. The silicide strap provides an electrical connection between the gate and the source drain region.
In one embodiment, the silicide strap is formed by a method that includes the steps of (1) implanting a semiconductor material, such as silicon, into upper surfaces of the gate, the dielectric spacer, and the source/drain region, (2) depositing a refractory metal over the implanted semiconductor material, and (3) reacting the refractory metal with the implanted semiconductor material, thereby forming the continuous silicide strap at the upper surfaces of the gate, the dielectric spacer and the source/drain region.
This method differs from the prior art, because the low resistance strap is formed on the surface of a spacer that is left intact instead of being removed by additional process steps prior to strap formation. In addition, the source/drain regions are completely formed prior to the formation of the strap, thereby eliminating problems associated with shallow diode junctions being formed under the strap.
The present invention will be more fully understood in view of the following description and drawings.
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“A 2.9 &mgr;m2Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 &mgr;m High Performance CMOS Logic”, Noda et al., 1997 IEEE.
Cao Wanqing
Cobert Dave
Lee Eric
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Loke Steven
Owens Douglas W.
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