Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-01-02
1999-01-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, 711460, G06F 1212
Patent
active
058600957
ABSTRACT:
A computer memory cache system that includes hardware (called a conflict cache) for short term tolerance and reduction of cache misses and including counters to enable software to detect and remove longer term cache misses through dynamic page remapping. In an example embodiment, when a conflict miss occurs for a low associativity cache, the address of the displaced item is saved in a content addressable memory and the corresponding data is saved in a data RAM. The operating system logically partitions the low associativity cache into bins, where the address range for a bin is a page or multiple pages. Every logical bin in the low associativity cache has a corresponding counter in the conflict cache. Each bin counter counts the number of conflict misses for the corresponding bin. When a bin counter exceeds a predetermined value, the operating system remaps a corresponding page. For a multiple level cache hierarchy, the top level cache is made a subset of the union of a lower level direct mapped cache and the conflict cache. This inclusion property prolongs the life of cache lines in the top level cache in the presence of conflict misses, improving the top level cache performance. In addition, the top level cache (and the conflict cache) may contain several lines that map to the same index in the lower level cache, thereby reducing the probability of thrashing due to the lower level cache.
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Iacobovici Sorin
Mulla Dean A.
Chan Eddie P.
Hewlett--Packard Company
Portka Gary J.
Winfield Augustus W.
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