Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With microwave gas energizing means
Reexamination Certificate
1999-01-11
2001-07-17
Mills, Gregory (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With microwave gas energizing means
Reexamination Certificate
active
06261406
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, the present invention relates to devices and methods used in dry etching a surface of a wafer or substrate in semiconductor processing, and more particularly, to a novel dry etch confinement device that takes advantage of the so-called “hollow cathode effect” for operative arrangement within a substrate etching chamber apparatus that can be incorporated into an integrated cluster tool platform, if desired; and a novel method of dry etching a surface of a wafer substrate using such a confinement device with an etchant gas.
Microelectronics is that area of electronics technology associated with the fabrication of electronic systems or subsystems using extremely small (microcircuit) components. Since semiconductor fabrication and processing is driven by the computer- electronics industry, the demands for greater capability and faster data processing of smaller-sized computerized systems result in a demand for smaller-and-smaller integrated circuit (IC) microcircuits. Thus, precision IC processing is ever more important in microcircuit wafer fabrication.
The use of silicon and its oxide, along with photolithography, in semiconductor wafer fabrication dates back to the 1950's. The substrate for a microelectronic circuit is the base upon which the circuit is fabricated. A substrate must have sufficient mechanical strength to support its circuit(s) during fabrication, and substrate electrical characteristics depend on the type of microcircuit being fabricated. In general, hybrid microcircuits are deposited on substrates, and monolithic integrated circuits are formed within substrates. The substrates used in building hybrids are usually dielectric materials such as ceramics, glasses, or single-crystal insulators; and in some cases conductors or semiconductors coated with a dielectric layer are used. The substrates used for monolithic integrated circuits are semiconductor (e.g. silicon, GaAs) wafers (which can provide both electrical and mechanical-support functions) sliced from large single crystals, except in the case of special fabrication processes like silicon on sapphire.
Microcircuit wafer fabrication generally starts with a substrate to which layers, films, and coatings (such as photoresist) can be added or created (e.g., when fabricating a MOS monolithic IC, a silicon oxide layer is created on top of the silicon wafer), and from which these added or created materials can be subtractively etched (e.g., as in dry etching). Throughout semiconductor wafer fab, various processes are used to “clean” the wafers so that surfaces are reproducible and stable (see, generally, “Microelectronics: Processing and Device Design” by Prof. Roy A. Coclaser, John Wiley & Sons (1980), pg. 82).
More-particularly, in silicon wafer production, a well known process called chemical mechanical polishing (CMP) is widely being used to create a more planar outer top surface. Many integrated circuit fabrication modules introduce topographic non- planarity onto the wafers top surface. Examples include the formation of metal interconnect lines by metal deposition and patterning using photolithography and reactive ion etching. The subsequent dielectric deposition process preserves this non-planarity of the wafer top surface but this non-planarity is undesirable for subsequent photolithography patterning steps. To solve this problem, the deposited oxide thickness is increased compared to the desired final oxide thickness, and then this additional oxide is removed by CMP. In the case of oxide CMP, the wafer is polished using a colloidal suspension of fine SiO
2
particles in an aqueous, alkaline “polishing” solution. The mechanical component of the polishing process causes material to be removed more rapidly from the high spots of the wafer surface which reduces the amplitude of any surface topography.
In the case of patterning (photo and etch) after dielectric deposition, the requirement for simultaneously clearing the circuit areas and the alignment marks makes dielectric etching difficult. For example, in dielectric via etching, it is difficult to develop an optimized etch process that simultaneously clears the vias and the alignment marks without over or underetching either. Even if an optimized dielectric etch process could be developed, certain thicknesses of dielectric over the alignment marks may create undesirable interference effects, making their recognition by the stepper alignment system difficult. This may necessitate the use of an extra photo-etch step to clear the dielectric over the alignment marks before attempting the patterning of the circuit. Thus it is advantageous to remove dielectric from over the alignment marks. The confinement device and associated method for selectively etching of the invention eliminates the need for an extra patterning step by using a two step etch that, first, clears out the alignment mark(s) in an etching chamber incorporating the novel confinement device and, then, performs a standard via etch in a subsequent conventional etch chamber.
Although CMP has a desired surface-planarization benefit (whether it is for dielectric or metal uniformity upon which successive layers can be built), an undesirable and costly side-effect of using CMP is that alignment marks required for subsequent photolithography steps are also “planarized”. When a subsequent metal layer is applied to the wafer above a planarized featureless surface, the alignment marks are no longer “visible” to the alignment sensors in the lithography tools, which require distinctive topography/contrast difference in the alignment mark scheme to operate. This is illustrated in
FIGS. 2A-B
, and associated background description in Column 2, of U.S. Pat. No. 5,705,320 issued to Hsu et al. which states that: “It is therefore essential that the IMD [inter-metal-dielectric layer 30] be cleared from the alignment mark areas and the metal layer from laser mark areas.” Good definition of alignment marks is necessary for proper pattern alignment in subsequent wafer fabrication steps.
Currently, to clear-out alignment marks/recesses filled-in after a planarization process, such as CMP, IC manufacturers often use a series of additional costly (complex and time-consuming) photolithography steps: Applying a marker clear-out photo resist (or photosensitive coating that adheres to the outer surface of the wafer), exposing the resist to ultraviolet light, developing the resist pattern, then etching the mark or recess using a plasma etching (e.g. reactive ion etching (RIE)) process, and finally adding a resist ash and cleaning step. Since the CMP process can be used several times throughout the fabrication of a single semiconductor wafer, and an alignment mark clear- out step is generally required after each CMP step to provide “redefinition” to every mark that has lost its distinctive recessed-topography, a single wafer can undergo several additional time-consuming photolithography clear-out steps. Therefore, in wafer fabrication, it is very desirable to find an alternative to having to perform (costly) photolithography alignment mark clear-out steps. The instant invention does just that.
U.S. Pat. No. 5,271,798 issued to Sandhu et al. In 1993, describes “the selective etching of tungsten by locally removing the tungsten from the alignment marks [normally a few-hundred microns in size] through wet etching without the need for any photo steps. Either before tungsten CMP or after, the wafers are flat aligned and tungsten etch solution is introduced through an enclosed etchant dispensing apparatus . . . [see column 2, lines 18-25].” After the wet etch, the etching byproduct is removed by suction and the wafer is cleaned by being rinsed in distilled water. “Wet etching” uses liquids (which have safety hazards and liquid waste disposal problems) and has limited uses in wafer fabrication.
FIG. 3 of U.S. Pat. No. 5,705,320 to the Hsu et al., mentioned above, shows a reticle 50 for a stepper which contains an image of the pattern for integrated circuit conta
Johnson Gregory A.
Jurgensen Charles W.
Taravade Kunal N.
LSI Logic Corporation
Mills Gregory
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