Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-05-04
1998-06-02
Harvey, Jack B.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395287, 395290, 711147, H01J 1300
Patent
active
057614512
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention concerns a configuration (or system) with several active (master) and passive (slave) bus users, each of which includes an allocated memory.
To allow hardware and software tasks to be performed simultaneously in the entire system, each memory in such a configuration has a shared memory area. A "memory area" is, for example, a data memory (RAM) or register of the bus users to which each active bus user has read or write access. The contents of the memory area of each bus user must be identical, and changes in the contents must occur synchronously, taking into account the different propagation times in the system.
German Patent Application No. P 42 19 005.3 proposes a computer system with a plurality of interconnected processors, each of which is allocated a memory. The memories have at least one common memory area accessed by the processors. The common memory area is used for initiating a change of state of the processors or for a synchronous processing of processor tasks. The computer system of the 42 19 005.3 application does not refer to the type of configuration of the present invention.
The goal of the present invention is to provide a configuration according to the above mentioned type, in which the contents of the memory area is changed quasi-synchronously.
SUMMARY OF THE INVENTION
To achieve this goal, the present invention provides a novel configuration having at least one active bus user with an allocated memory having a memory area, at least one passive bus user with an allocated memory having a memory area, a system bus, an arbiter, and a control line. The system bus couples the active user(s) and the passive user(s) with address, data, and control lines. The arbiter manages access to the system bus. Each of the bus users can read access its own memory area. Each of the active bus users can write access each memory area. The control line transfers a control signal which indicates to an active user attempting to access a memory area that data is being written into memory areas. The control signal has a dominant state and a recessive state. All bus users generate a dominant state outside an access cycle, while during an access cycle to memory areas, only bus users having memory areas in which the data has not yet been written generate a dominant state.
In a preferred embodiment of the present invention, the passive bus user generates a dominant state of the control signal during a read access by it.
In a preferred embodiment of the present invention, the arbiter blocks access to the system bus by other bus users before a read or write access by the active bus user.
In a preferred embodiment of the present invention, the bus users may be modules in one or more subracks. In this embodiment, the control line preferably runs through all of the subracks.
The system of the present invention may also include modules that cannot generate control signals. Such modules should include an adaptor device for generating a control signal assuming a recessive state and having a delay equal to at least a longest duration of an access cycle.
The control line may be provided with a pull-up resistor. The bus users may be coupled with the control line via an open collector output.
The configuration according to the present invention can be used, in particular, in a memory-programmable control, and preferably in a memory-programmable control with a central device and at least one extension device, connected, via a system bus and a connection cable, with the control line.
BRIEF DESCRIPTION OF THE DRAWING
The present invention, as well as its implementation and advantages, are described in detail using the drawing that illustrates an embodiment of the present invention.
FIG. 1 is a block diagram illustrating a configuration according to the present invention.
FIG. 2 is a timing diagram of the relevant control signals of the present invention.
DETAILED DESCRIPTION
In FIG. 1, active and passive bus users are coupled with each other, via a system bus SYB having par
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Abert Michael
Block Siegfried
Bozenhardt Johannes
Leigsnering Franz
Pfatteicher Werner
Harvey Jack B.
Phan Raymond N
Siemens Aktiengesellschaft
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