Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
1999-09-23
2001-09-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S040000
Reexamination Certificate
active
06288566
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to reconfigurable logic chips.
Reconfigurable logic chips, such as field programmable gate arrays (FPGAs) have become increasingly popular. Such chips allow logic to implement different circuits at different times.
FPGAs are being increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs) while providing most of the performance advantages of a dedicated hardware solution.
One growingly popular use of FPGAs is referred to as reconfigurable computing. In reconfigurable computing, hardware logic functions are loaded into the FPGA as needed to implement different sections of a computationally intensive code. By using the FPGAs to do the computational intensive code, advantages are obtained over dedicated processors. Reconfigurable computing is being pursued by university researchers as well as FPGA companies.
Typically, in order to change configurations, FPGAs load new configuration data for different functional units from off-chip. This can be time consuming and may reduce the efficiency of a reconfigurable computing system. It is desired to have an improved reconfigurable chip for reconfigurable computing.
SUMMARY OF THE PRESENT INVENTION
The present invention comprises a configuration state memory for use on a reconfigurable chip. The configuration state memory stores multiple configurations which can be used to configure a functional block unit into a variety of functions. By storing multiple configurations local to the functional block unit in the configuration statement memory, the system of the present invention allows for dynamic switching between different functions in the functional block unit. This improves the efficiency of reconfigurable computing system. Additional configurations need not be loaded from off-chip to switch the function of a functional unit.
In a preferred embodiment, the functional block units have reconfigurable elements within them which are reconfigured by the configuration lines coming from the configuration state memory. The functional block units can implement a variety of functions such as add, shift, subtract, etc.
In one embodiment, the configuration state memory has a relatively few address bits and a greater number of output configuration lines. In one preferred embodiment, the configuration state memory has a three-bit address and a forty-plus bit configuration output. The number of output bits can be varied depending on the complexity of the data path unit. A three-bit address allows for eight different configurations to be stored locally near the functional block units. In one embodiment of the present invention, the memory in the configuration state memory is arranged into a background plane and a foreground plane. The arrangement into the background plane and the foreground plane allows a background plane to be loaded onto the chip without affecting the operation of the configuration state memory.
The configuration state memory may be a part of a control fabric unit. The configuration state memory is addressed by a state machine that allows the addresses for the configuration state memory to be produced locally on the reconfigurable chip. In this way, a configuration of the state machine can address multiple stored data path unit configurations in the configuration state memory. The configuration state memory preferably stores enough configurations for the data path unit that the data in the configuration state memory need not be changed every time the state machine configuration is changed. The state machine can receive inputs from functional block and the CPU on the reconfigurable chip as well as being configured from off-chip. The state machine can be implemented using a reconfigurable programmable sum of products (PSOP) generator.
REFERENCES:
patent: 5426378 (1995-06-01), Ong
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5760602 (1998-06-01), Tan
patent: 5796269 (1998-08-01), New
patent: 6005865 (1999-12-01), Lewis et al.
patent: 6018559 (2000-01-01), Azegami et al.
patent: 6091263 (2000-07-01), New et al.
Hanrahan Shaila
Phillips Christopher E.
Burns Doane Swecker & Mathis
Chameleon Systems, Inc.
Cho James H.
Tokar Michael
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