Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-07
2001-04-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06216259
ABSTRACT:
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark office patent file or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
The present invention generally relates to configuration of programmable logic devices, and more particularly, to run-time reconfiguration of programmable logic devices.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. In general, the use of FPGAs continues to grow at a rapid rate because FPGAs permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their reprogrammability. The capabilities of and specifications for XILINX FPGAs are set forth in “The Programmable Logic Data Book,” published in 1998 by XILINX, Inc., the contents of which are incorporated herein by reference.
The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems. However, scarcity of software that supports RTR is believed to be one reason that RTR has been outpaced by research in other areas of reconfigurable computing.
Whereas with traditional configuration of FPGAs the time taken to generate a programming bitstream is generally not real-time critical, with RTR systems, the time required to generate the programming bitstream may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured. Thus, it may be acceptable to take hours to generate a programming bitstream using traditional configuration methods. In a run-time environment, however, it is expected that the reconfiguration process require no more than a few seconds or even a fraction of a second.
Reconfiguration of an FPGA may include reparameterizing various logic cores and rerouting connections between the logic cores. Parameterizable cores permit the user to enter information about the desired core, from which a customized circuit conforming to this information is constructed. An example of a parameterizable core is an adder core to produce an adder circuit. Example parameters include the size, for example, 4 bit, 8 bit, or 16 bit, and serial versus parallel.
Once reparameterized, the connections between cores and placement on the FPGA must be established. Routers in a traditional configuration process generally route connections for all the circuit elements. That is, these routers define connections for all the circuit elements in a design. Therefore, in an RTR environment, traditional reparameterization and routing methods are inappropriate given the real-time operating constraints.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, the invention comprises methods and systems for configuration and run-time reconfiguration of programmable logic devices using routing cores. In one embodiment, a method is provided for configuration of a programmable logic device, where the programmable logic device is coupled to a processor. A library that comprises logic core generators and one or more router core generators is used for configuration, and the method comprises executing a program on the processor, the program including instructions that select functions to be provided by the programmable logic device. One or more of the logic core generators, in response to the program, generate logic core definitions that define at least two logic cores; and the router generators, in response to the program, generate at least one router core definition that defines a coupling of the logic cores in the programmable logic device. From the logic and router core definitions, programming bits are generated and the programmable logic device is then loaded with the programming bits.
In another embodiment, a system for run-time reconfiguration of a programmable logic device is provided. The system comprises a processor arranged to host a program, where the program includes instructions that select functions to be provided by the programmable logic device. A library of logic core generators and router core generators is accessible to the application program and executable on the processor; and a programming bit generator is accessible to the application program for generation of programming bits in response to output of the logic core and router core generators. A programmable logic device is coupled to the processor and configurable with the programming bits.
An apparatus for configuration of a programmable logic device that is coupled to a processor is provided in another embodiment. The apparatus comprises: means for selecting functions to be provided by the programmable logic device with program instruction references to a library of logic core and router core generators; means for generating logic core definitions; means for generating router core definitions that define couplings between the logic cores in the programmable logic device; means for generating programming bits from the logic core definitions and router core definition; and means for loading the programmable logic device with the programming bits.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
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Guccione Steven A.
Levi Delon
Garbowski Leigh Marie
Maunu LeRoy D.
Smith Matthew
Xilinx , Inc.
Young Edel M.
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