Configuration of gate to drain (GD) clamp and ESD protection...

Details Configuration of gate to drain (GD) clamp and ESD protection... Configuration of gate to drain (GD) clamp and ESD protection...

2011-03-08

2011-03-08

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S551000

Reexamination Certificate

active

07902604

ABSTRACT:
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.

REFERENCES:
patent: 5536958 (1996-07-01), Shen et al.
patent: 2009/0128223 (2009-05-01), Lui et al.

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