Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2002-08-07
2004-08-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S786000, C257S784000, C257S737000, C257S776000
Reexamination Certificate
active
06777815
ABSTRACT:
This application incorporates by reference Taiwanese application Serial. No. 90121365, filed on Aug. 29, 2001
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of packaging integrated circuits, particularly to a configuration of a redistribution layer applied in the core of a flip-chip with power bumps and ground bumps thereon.
2. Description of the Related Art
With the rapid developments in ULSI manufacturing, the function of single chip is accordingly increased, which promotes advances in packaging methods. The traditional packaging method, utilizing lead frames to connect the O/I connection, bonding pad, or wire bonding pad, and enveloping chips with ceramic or epoxy, has been proven to be difficult for the packaging of VLSI chips. It goes without saying that the traditional packaging method certainly can not fulfill the demands of the next generation of ULSI chips.
Traditionally, to prevent the shifting of bonding wires during the step of injecting the plastic material or the lengthening of the bonding wires, the bonding pads have been designed on the periphery of the chips. Therefore, longer conductive traces are needed to connect the device to the bonding pads. Moreover, as the trend of chip advances toward higher speeds and higher capabilities, the number of I/O connections is rapidly being increased. However, the high inductance created in the connection of bonding pads and bonding wires obstructs the high-speed operation of the chips.
To solve the problems described above, a packaging method for a flip-chip has been recently developed.
FIG. 1
illustrates the conductive bumps (
24
) on the surface of a chip (
20
). The conductive bumps (
24
) are evenly disposed on the chips (
20
) with an array arrangement, but are not limited to the periphery of the chip (
20
) or the outside of the device area. By flipping the chip (
20
), the conductive bumps (
24
) are mounted to the bump pads (
28
) (or flip-chip bump pads) on the substrate (
26
). The bump pads (
28
) on the substrate (
26
) are also arranged in an array and each corresponds to the conductive bumps (
24
) on the chip (
20
).
In the inner core of the chip, the design for the flip-chip type does not differ widely with that for the wire bonding type. In the wire bonding type, the devices may not be positioned under the bonding pads. Therefore the bonding pads are positioned on the periphery of the chip, while a passivation layer covers the remaining area of the chip. In the flip-chip type, a metal layer is further provided on the passivation layer of the wire bonding type and then a lithography and an etching method are carried out thereby forming a redistribution layer. The bonding pads on the periphery of the chip are connected to the conductive bumps in the core of the chip. Therefore, the present circuit design of the wire bonding type is also applied in the design of flip-chips.
According to a conventional way, all of the conductive bumps including ground bumps, power bumps or signal bumps are mixed in the array arrangement, which increases the length of conducting traces for the signal bumps and thus lowers the speed of the operation. In U.S. Pat. No. 5,952,726, the signal bumps are positioned on the edge of the chip. The power bumps (VDD) and the ground bumps (VSS) are evenly distributed in the core of the chip, as shown in FIG.
2
. The power traces (
60
) and the ground traces (
70
) are provided between the conductive bumps. The power bumps (VDD) and the ground bumps (VSS) are respectively connected to the power traces (
60
) and the ground traces (
70
) by conductive traces (
65
) and conductive traces (
75
) respectively.
In U.S. Pat. No. 5,952,726, in the bump arrangement, however, two defects remain unsolved. The impedance due to conductive traces is high and the bump density is low. In the redistribution layer, connecting lines are required for connecting the power and ground traces to the power and ground bumps, respectively. In addition, when the conductive traces of all layers are projected onto a phantom plane parallel to the layers, the possibility of projections of the traces to cross each other decreases due to the parallel arrangement of the power bus and the ground bus, which means more complex interconnecting traces or additional interconnecting traces are needed. The impedance increases when the length or the complexity of conductive traces increases. The bump density, which is the number of bumps that can be arranged in the same area, is not high enough in this arrangement because some spaces between two adjacent rows of bumps are reserved for the conductive traces. Therefore, there is a need to improve these defects.
SUMMARY OF THE INVENTION
The object of this invention is to provide a configuration of conductive bumps requiring shorter conducting traces and having less impedance on the chip.
Another object of the present invention is to provide slanted conducting traces on the redistribution layer to increase the probability that the power bus and ground bus intersect with the power traces and ground traces respectively. Still another object of the present invention is to provide a redistribution layer having a high bump density.
The present invention discloses a configuration of conductive bumps and a redistribution layer for a flip chip. The first embodiment comprises: a plurality of power bumps and ground bumps disposed in hive-shaped arrangement on the core of a flip chip; a plurality of power lines slanted at 60-degree angle, relative to a horizontal line, for connecting power bumps; and a plurality of ground lines slanted at 60-degree angle, relative to a horizontal line, for connecting ground bumps. Therefore, the probability for the power traces and ground traces to intersect with the power bus and ground bus respectively is increased. The conductive bumps of the second embodiment are disposed in a checkerboard configuration. The conductive bumps of the third embodiment are disposed in a stagger arrangement, and the power bumps and ground bumps are respectively connected by power traces and ground traces, which are slanted at 45-degree angle, relative to a horizontal line. The power traces and the ground traces are in a redistribution layer.
REFERENCES:
patent: 5739587 (1998-04-01), Sato
patent: 5952726 (1999-09-01), Liang
patent: 6057596 (2000-05-01), Lin et al.
patent: 6191479 (2001-02-01), Herrell et al.
Flynn Nathan J.
Mandala Jr. Victor A.
Troxell Law Office PLLC
Via Technologies Inc.
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