Configuration network for a configurable IC

Details Configuration network for a configurable IC Configuration network for a configurable IC

2006-03-13

2008-10-28

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

07443196

ABSTRACT:
Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

REFERENCES:
patent: 5426378 (1995-06-01), Ong
patent: 5521835 (1996-05-01), Trimberger
patent: 5600263 (1997-02-01), Trimberger et al.
patent: 5610829 (1997-03-01), Trimberger
patent: 5629637 (1997-05-01), Trimberger et al.
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5654650 (1997-08-01), Gissel
patent: 5701441 (1997-12-01), Trimberger
patent: 5825662 (1998-10-01), Trimberger
patent: 6084429 (2000-07-01), Trimberger
patent: 6404224 (2002-06-01), Azegami et al.
patent: 6430736 (2002-08-01), Levi et al.
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6614703 (2003-09-01), Pitts et al.
patent: 6829756 (2004-12-01), Trimberger
patent: 6894527 (2005-05-01), Donlin et al.
patent: 7010667 (2006-03-01), Vorbach et al.
patent: 7064577 (2006-06-01), Lee
patent: 7085858 (2006-08-01), Fox et al.
patent: 7112992 (2006-09-01), Guzman et al.
patent: 7138827 (2006-11-01), Trimberger
patent: 7231339 (2007-06-01), Nemecek et al.
patent: 7233169 (2007-06-01), Vadi
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2002/0089349 (2002-07-01), Barbier et al.
Claims of Related Cases as of Jan. 15, 2008, Claims of Related Cases with U.S. Appl. No. 11/375,562, U.S. Appl. No. 11/375,362, U.S. Appl. No. 11/375,370, U.S. Appl. No. 11/375,369, U.S. Appl. No. 11/375,364, and U.S. Appl. No. 11/375,561. The above-mentioned related cases (1) were listed as related cases in the Notice of Related Cases dated Sep. 16, 2006 and (2) have the same specification and drawings as the present application.
Claims of Related Cases as of Dec. 14, 2007, Claims of Related Cases with U.S. Appl. No. 11/375,562, U.S. Appl. No. 11/375,362, U.S. Appl. No. 11/375,370, U.S. Appl. No. 11/375,369, U.S. Appl. No. 11/375,364, and U.S. Appl. No. 11/375,561. These cases (1) were listed as related cases in the Notice of Related Cases dated Sep. 16, 2006 and (2) have the same specification and drawings as the present application.
Non-Final Office Action for U.S. Appl. No. 11/375,362, (mailing date) Jul. 18, 2007, Redgrave, et al., Non-Final Office Action of Related Application.
Non-Final Office Action for U.S. Appl. No. 11/375,369, (mailing date) Aug. 21, 2007, Redgrave, et al., Non-Final Office Action of Related Application.
Non-Final Office Action for U.S. Appl. No. 11/375,364, (mailing date) Jul. 6, 2007, Hutchings, et al., Non-Final Office Action of Related Application.
Altera Corp., “Section V. In-System Design Debugging,”Quartus II Handbook, May 2007, pp. 1-150.
Amerson, R., et al., “Teramac—Configurable Custom Computing,” 1995 Month N/A, pp. 32-38, Palo Alto, CA, USA.
Arnold, J., “The Splash 2 Software Environment,”IDA Supercomputing Research Center, 1993 Month N/A, pp. 88-93, Bowie, MD, USA.
Arnold, J., et al., “Splash 2,”Supercomputing Research Center, 1992 Month N/A, pp. 316-322, Bowie, MD, USA.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, 1995 Month N/A, pp. 487-494, Portland, Oregon, USA.
Comptom, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34., No. 2, New York, New York.
Graham, P., “Logical Hardware Debuggers For FPGA-Based Systems,”A Dissertation Submitted to the Faculty of Brigham Young University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Brigham Young University, 2001 Month N/A, pp. 1-266.
Hanono, S., “InnerView Hardware Debugger: A Logic Analysis Tool for the Virtual Wires Emulation System”,Submitted to the Department of Electrical Engineering and Computer science in Partial Fulfillment of the Requirements for the Degree of Master of Science at the Massachusetts Institute of Technology, Feb. 1995, pp. 1-59.
Hutchings, B., “Unifying Simulation and Execution in a Design Environment for FPGA Systems,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Feb. 2001, pp. 201-205, vol. 9, No. 1, IEEE.
Hutchings, B., et al., “A CAD Suite for High-Performance FPGA Design,”Defense Advanced Research Projects Agency, NPL Date Unknown, pp. 1-16, Provo, UT, USA.
Hutchings, B., et al., “Designing and Debugging Custom Computing Applications,”IEEE Design&Test of Computers, Jan. 2000, pp. 20-28.
Trimberger, S., “Effects of FPGA Architecture on FPGA Routing,”32ndACM/IEEE Design Automation Conference, Jun. 1995, ACM.
Vuillemin, J., et al., “Programmable Active Memories: Reconfigurable Systems Come of Age,” 1994 Month N/A, pp. 1-15.
Xilinx, Inc., “ChipScope ProSoftware and Cores User Guide,” Jan. 10, 2007, pp. 1-206, Xilinx Inc.
Xilinx, Inc., “Virtex-5 FPGA,” Configuration User Guide, Feb. 2007, pp. 1-154, Xilinx, Inc.

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