Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1995-08-18
1997-02-04
Hudspeth, David R.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 41, 326 93, H03K 19177
Patent
active
056002637
ABSTRACT:
A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.
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Carberry Richard A.
Johnson Robert A.
Trimberger Stephen M.
Wong Jennifer
Harms Jeanette S.
Hudspeth David R.
Xilinx , Inc.
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