Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-03-21
2003-09-02
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S046000, C714S725000, C714S726000
Reexamination Certificate
active
06614259
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to integrated circuits and techniques for configuring integrated circuits. In particular, the invention relates to a configurable memory that is particularly useful for storing information used in the configuration of programmable logic devices (PLDs). For example, the invention provides a device capable of interfacing with the Altera Flex™ 10K and Flex™ 8K lines of PLDs. However, a device designed using the principles of the present invention will find beneficial use in storing information for a variety of purposes and interfacing with a variety of devices.
PLDs are well known in the industry. They allow designers to use off-the-shelf parts to perform specialized logic functions. A PLD is an integrated circuit which may be customized by the designer for different logical functions. As such, PLDs combine the logistical advantages of standard, fixed, integrated circuits, with the architectural flexibility of custom-made devices. By using these devices, custom logic functions can be designed and fabricated in-house, while eliminating the long engineering lead times, high tooling costs, complex procurement logistics and dedicated inventory problems associated with custom devices. Furthermore, the design can be easily changed without upsetting design schedules and purchase agreements.
When a typical PLD is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The device must first be configured. PLDs often comprise a plurality of generic logic blocks which may be arbitrarily programmed and interconnected to each other. Often, they are implemented using volatile memory such as an SRAM. Volatile memory loses its configuration upon termination of power to the system. Alternatively, a PLD may be implemented with nonvolatile memories such as Erasable Programmable Read Only Memories (EPROMs), Electronically Erasable Programmable Read Only Memories (EEPROMs), fuses, and antifuses which retain their configuration upon termination of power.
If the programmable elements used are volatile memories, the memory cells must be configured upon system power-up in order for the device to operate as desired. This is typically done by loading configuration data from an external source into the PLD. The external source may be, for example, a nonvolatile memory. Often, the configuration data is stored in a configuration memory. A configuration memory is a memory capable of storing information. Configuration of the PLD is accomplished by transferring the configuration data from the configuration memory to the PLD. Another method of performing the configuration is to transfer the data from external memory by means of an intelligent host such as a CPU, system controller, and the like.
The present invention recognizes that an improved configuration memory is desirable. As programmable logic devices and the systems within which they operate become more complex, the configuration memories, and techniques for using them must improve. Today's programmable logic devices are becoming larger and more complex. Consequently, more configuration data is needed to configure them. Speed and flexibility of the configuration process is becoming of increasing concern. Furthermore, new techniques for configuring the devices require advances over the current state of the art in configuration memories.
There is thus a need for an improved configuration memory.
SUMMARY OF THE INVENTION
The present invention provides a configuration memory for use in storing information The configuration memory comprises a memory array in which the information is stored, a data-out port through which the information is transferred, and JTAG circuitry capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of the configuration memory according to the JTAG instructions. The JTAG port is defined by the Joint Test Action Group interface standard (JTAG Standard). The JTAG standard is described in IEEE Standard 1149.1-1990,
IEEE Standard Test Access Port and Boundary
-
Scan Architecture,
which is incorporated herein by reference for all purposes.
In a preferred embodiment, the information stored in the configuration memory is configuration data for use in configuring a programmable logic device.
In another preferred embodiment, resistors are provided within a common physical package with the configuration memory to hold some of the control signals at a desired logic level. These resistors are able to be selectively decoupled from the system to allow backward compatibility with previous devices.
A method for configuring a programmable logic device is also provided. The method includes the steps of providing a configuration memory which has a memory array and JTAG circuitry capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of the configuration memory according to the JTAG instructions, programming the memory array with configuration data, and transferring the configuration data to the programmable logic device. In a preferred embodiment of the present invention, the configuration memory is programmed by having data transferred to it through the JTAG port. Another preferred embodiment transfers data from the configuration memory to the programmable logic device upon receipt of a JTAG instruction.
A method for programming a configuration memory in-system is also provided. The method includes the steps of sending a JTAG instruction to the JTAG port of the configuration memory and transferring the configuration data into the memory array of the configuration memory through a JTAG port.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
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“The Programmable Logic Data
Couts-Martin Chris
Herrmann Alan
Altera Corporation
Chang Daniel
Townsend and Townsend / and Crew LLP
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