Configuration memory implementation for LUT-based...

Details Configuration memory implementation for LUT-based... Configuration memory implementation for LUT-based...

2007-02-27

2007-02-27

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S038000, C326S039000, C326S040000, C326S041000, C326S047000, C716S030000

Reexamination Certificate

active

10507813

ABSTRACT:
A reconfigurable processing unit (1) is described which comprises, data flow controlling elements (10), data manipulating elements (20), a configuration memory unit (30) comprising a plurality of memory cells (31a, . . . ) for storing settings of the data flow controlling elements (10) and an address decoder (40) for converting an address into selection signals for the memory cells (31a, . . . ). The reconfigurable processing unit of the invention is characterized in that the address decoder (40) is shared between the configuration memory unit (30) and a further memory unit (20), or between two configuration memory units (30, 30′). This provides for a reduction in memory area of the reconfigurable processing unit (1).

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