Configuration logic to eliminate signal contention during reconf

Details Configuration logic to eliminate signal contention during reconf Configuration logic to eliminate signal contention during reconf

1995-01-20

1997-01-07

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, 326 46, 377 69, 377 75, H03K 19173, G11C 1928, G11C 1900

Patent

active

055921051

ABSTRACT:
A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

REFERENCES:
patent: 4975640 (1990-12-01), Lipp
patent: 5282234 (1994-01-01), Murayama et al.
patent: 5363424 (1994-11-01), Fujisawa
IBM Technical Disclosure, vol. 28, No. 1, Jun. 1985, pp. 44-46.

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