Configuration logic to eliminate signal contention during reconf

Details Configuration logic to eliminate signal contention during reconf Configuration logic to eliminate signal contention during reconf

1997-04-23

1998-06-23

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, 326 46, 365240, H03K 19177, G11C 804

Patent

active

057709513

ABSTRACT:
A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

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