Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-12-25
2007-12-25
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000, C714S027000, C714S028000, C714S031000, C714S045000, C716S030000, C716S030000
Reexamination Certificate
active
10850123
ABSTRACT:
An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTAG-compatible bitstream that can be used by the processor's test circuitry to access and/or control the processor's resources at any time, thereby allowing the embedded processor's resources to be accessed and controlled during FPGA configuration operations before the processor has been initialized to an operational state without using an external configuration tool. For some embodiments, the formatting circuit is a state machine that formats soft data such as firmware code, software programs, processor commands, and the like received from the external storage device into a JTAG-compatible bitstream that can be loaded into and/or used to access the resources of the embedded processor via the processors' test circuitry.
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Beausoliel Robert
Manoskey Joseph D
Paradice III William L.
Xilinx , Inc.
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