Configuration interface to stacked FPGA

Details Configuration interface to stacked FPGA Configuration interface to stacked FPGA

2011-07-05

2011-07-05

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

07973555

ABSTRACT:
A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

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