Configuration for self-referencing ferroelectric memory cells

Details Configuration for self-referencing ferroelectric memory cells Configuration for self-referencing ferroelectric memory cells

2000-10-20

2001-11-13

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S065000

Reexamination Certificate

active

06317356

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention concerns a configuration for self-referencing a ferroelectric memory cell which is formed of a ferroelectric storage capacitor with a cellplate and a transfer transistor. The ferroelectric memory cell is provided in a memory cell array controlled via word lines and bit lines. The ferroelectric storage capacitor is provided between a cellplate line and the transfer transistor. In order to perform a self-referencing with an evaluator circuit, the memory cell is written-in and read-out again after a read process for determining a reference voltage.
As illustrated in
FIG. 18
, in prior art ferroelectric memories memory cells of ferroelectric storage capacitors Cs
0
, Cs
1
and transfer transistors T are provided between bit lines BL and word lines WL
0
, WL
1
. The cellplates of the memory cells can be connected to one another either parallel to the bit lines, as shown in
FIG. 18
, or parallel to the word lines WL
0
, WL
1
, but can also be provided such that they are connected in both directions.
On reading out the content of such a ferroelectric memory cell the bit line BL acquires a read voltage of U
L1
or U
L0
depending on whether a “1” or a “0” is read out (cf. also FIG.
17
). The voltage difference between the read voltages U
L1
and U
L0
is normally in the region of 100 mV.
The task of an evaluator circuit—also known as an “evaluator”—is to detect the read voltage U
L
on the bit line BL as “1” (i.e. U
L1
) or “0” (i.e. U
L0
) and to amplify it accordingly. The detection takes place through comparison of the read voltage U
L
with a reference voltage U
R
. If the read voltage is greater than the reference voltage U
R
, a “1” is detected; if it is smaller than the reference voltage U
R
a “0” is detected.
In the prior art, in most cases this is achieved through generating the reference voltage on a reference bit line {overscore (BL)} by reading out the content of a reference cell formed of a ferroelectric storage capacitor C and a transfer transistor T, whereby this reference cell is dimensioned and/or connected such that the reference voltage U
R
is produced in a suitable way.
It is also important that the reference voltage U
R
be exact to within a few mV and as close as possible to the middle position between the read voltages U
L1
for “1” and U
L0
for “0”.
This requirement, however, causes considerable problems in the generation of the reference voltage U
R
during operation of the ferroelectric memory:
(a) The read voltage U
L
of the ferroelectric memory cells and the reference voltage U
R
of the reference cells are already scattered simply as a result of the manufacturing process, which cannot proceed in exactly the same way for all memory cells.
(b) Depending on the number of write and read cycles, the electrical characteristics of the ferroelectric memory cells and the reference cells change as a result of the “aging” characteristics (hysteresis curve becomes narrower), “fatigue” (hysteresis curve rotates) and “imprint” (hysteresis curve is displaced up or down), whereby this aging process progresses differently for the two types of cell.
As a consequence of the above problems (a) and (b), the read voltage U
L
and/or the reference voltage U
R
can be displaced to such an extent that correct evaluation of the read voltage U
L
as a “1” or a “0” during operation of the ferroelectric memory is no longer possible.
In order to avoid the above difficulties, a self-referencing of a memory cell is described in the article “A Self-Reference Read Scheme for a 1T/1C FeRAM”, by J. Yamada et. al., 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 238 and 239, according to which the problem of differential aging of a memory cell and a reference cell is avoided. In this conventional self-referencing method, however, circuit measures such as different bit line capacities or evaluator circuits are used for generating the reference voltage, which results again in a dependence on the aging of the memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for self-referencing a ferroelectric memory cell which overcomes the above-mentioned disadvantages of the heretofore-known configurations of this general type and in which there is no dependency on the aging of the memory cell and for which the hysteresis range is utilized as much as possible for a determination of the reference voltage.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for self-referencing a memory cell, including:
a ferroelectric memory cell including a ferroelectric storage capacitor and a transfer transistor, the ferroelectric storage capacitor having a cellplate;
a bit line connected to the ferroelectric memory cell, the bit line being precharged with a first voltage having a first voltage value and subsequently with a second voltage having a second voltage value, the first and second voltages being opposite and different from one another;
a cellplate line, the ferroelectric storage capacitor being connected between the cellplate line and the transfer transistor;
a first capacitor and a second capacitor, the first capacitor temporarily storing a first read-out voltage value read from the ferroelectric memory cell while the bit line is precharged with the first voltage value, and the second capacitor temporarily storing a second readout voltage value read from the ferroelectric memory cell after the bit line is precharged with the second voltage value; and
an evaluator circuit connected to the first capacitor and to the second capacitor, the evaluator circuit receiving the first and second read-out voltage values after being temporarily stored by the first and second capacitors, the evaluator circuit comparing the first and second read-out voltage values for determining a stored cell content by self-referencing the ferroelectric memory cell.
In other words, the object of the invention is achieved with a configuration in which the memory cell can be read-out in a successive manner, while the bit line is precharged to two different voltages with a first and respectively a second voltage value, and each of the thus determined voltage values can be stored in a first and respectively a second capacitor before it is fed to the evaluator circuit.
In a first embodiment the cellplate line can be supplied with a fixed supply voltage, whereby the cellplate can be configured connected or coherent over the entire memory array formed from the memory cells, or, in a different embodiment, can have applied to it a voltage of a second or first voltage value if a voltage with the first or second voltage value is applied to the bit line. The second embodiment of a pulsed cellplate line has the advantage of preventing the occurrence of parasitic diodes in the memory cells.
In the case of pulsed cellplates, these can be connected together in lines parallel to the bit lines, whereby the reference voltage is available on the cellplate line.
Alternatively, it is possible to connect the cellplates together in lines parallel to the word lines and to extract the reference voltage on the bit line.
In accordance with another feature of the invention, the transfer transistor is blocked after the bit line is precharged with the first voltage.
In accordance with yet another feature of the invention, a respective one of the cellplate lines is used jointly by respective two of the bit lines.
In accordance with yet a further feature of the invention, the bit lines are crossed at least once with the cellplate lines.
In accordance with another feature of the invention, the bit line is precharged with a supply voltage as the first voltage and with 0 V as the second voltage.
In accordance with yet another feature of the invention, a memory cell array is formed from the ferroelectric memory cells, and the memory cell array is controlled by the word lines and the bit lines.
In contrast to the method of self-referencing according to the teaching of Yam

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