Configuration for fuse initialization

Details Configuration for fuse initialization Configuration for fuse initialization

2001-10-16

2003-08-05

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S189050, C365S230080

Reexamination Certificate

active

06603699

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a configuration for fuse initialization having at least one fuse bank which has a number of fuses in which redundant information is stored. The fuse bank can be read by a first and a second initialization signal, which are produced by a generator device. In each case one latch is associated with each fuse. The term “fuses” is in this case also intended to mean antifuses. The invention is preferably used in a memory whose memory cell array is subdivided into quadrants along which the fuse banks extend.
Redundant information that is stored in fuses is read to latches (locking elements) upon activation or start-up of a memory, for example a DRAM (Dynamic Random Access Memory). These latches buffer-store the redundant information and are located immediately adjacent to the fuses. In this case, each fuse has an associated latch.
Two initialization signals are required to read in redundant information, namely a first initialization signal bFPUP (bar fuse power up), which is an enabled signal, and a second initialization signal, FPUN, which is a control signal for latching in the redundant information and consists of a pulse which allows the redundant information to be buffer-stored in the latches for its duration.
FIG. 4
schematically shows a memory having a memory cell array including four quadrants Q
1
to Q
4
, and fuse banks
5
to
12
that are located between these quadrants Q
1
to Q
4
. The fuse banks
5
and
6
are associated with the quadrant Q
1
, while the fuse banks
7
and
8
are associated with the quadrant Q
2
, the fuse banks
9
and
10
are associated with the quadrant Q
3
, and the fuse banks
11
and
12
are associated with the quadrant Q
4
. In this case, the fuse banks
5
and
6
are located along two sides of the quadrant Q
1
, which are opposite the adjacent quadrants Q
4
and Q
2
and spaced away by a gap. A corresponding situation applies to the fuse banks
7
and
8
with respect to the quadrant Q
2
, to the fuse banks
9
and
10
with respect to the quadrant Q
3
, and to the fuse banks
11
and
12
with respect to the quadrant Q
4
. The fuses in the fuse banks
5
to
12
are in this case each associated with individual segments or arrays of the quadrants Q
1
to Q
4
.
FIG. 5
shows a fuse F with an associated latch L. The fuse F is connected in series with a series circuit, which includes an n-channel MOS transistor T
1
and a p-channel MOS transistor T
2
. The combination of the series circuit and the fuse F is connected between a fixed potential (frame or ground) and a supply voltage Vint. The first initialization signal bFPUP is applied to the gate of the transistor (T
2
), while the second initialization signal (FPUN) is applied to the gate of the transistor T
1
.
The node between the two transistors T
1
and T
2
is connected to the input of a first inverter I
1
and to the output of a second inverter I
2
that is downstream from the first inverter I
1
. In addition, the output of the first inverter I
1
is connected to the control input of a first controlled switch S
1
, while the output of the second inverter I
2
is connected to the control input of a second controlled switch S
2
.
A first signal A
1
is applied to the input of the first switch S
1
, while a second signal A
2
is applied to the input of the second switch S
2
.
FIG. 6
shows the profile of the supply voltage Vint, the profile of the first initialization signal bFPUP, and the profile of the second initialization signal FPUN as a function of time T.
When the supply voltage Vint is switched on, that is to say is high, the transistor T
2
is switched on, while the transistor T
1
is still switched off, since both signals bFPUP and FPUN are low. The supply voltage Vint is thus applied to the input of the latch L, so that its pre-initialization takes place. If the first initialization signal bFPUP then changes to high (flank F
2
), the transistor T
2
then is switched off. The latch L is thus disconnected from the supply voltage Vint. Once the second initialization signal, or pulse, FPUN has been switched on (flank F
3
), the transistor T
1
is switched on, while the transistor T
2
is switched off and the fuse information from the fuse F is thus supplied to the latch L. Depending on the content of this information (“1”) or (“0”), the switch S
1
is switched on, while the switch S
2
is switched off, or the switch S
1
is switched off while the switch S
2
is switched on. This writing process for the fuse information is terminated with the end of the pulse FPUN (flank F
4
). The signal A
1
or the signal A
2
is thus produced at an output A of the switches S
1
and S
2
, depending on the fuse information for the fuse F.
FIG. 7
shows one possible signal profile, which occurs when the first initialization signal bFPUP starts up together with the supply Vint. In this case, the pre-initialization of the latch L takes place on the trailing edge (flank F
1
) of the signal (bFPUP).
The two initialization signals bFPUP and FPUN must be supplied to all of the fuses in the fuse banks
5
to
12
upon activation of the memory, so that these fuses can read their respective information to the associated latches. Each individual fuse F has an associated latch L of the type shown in FIG.
5
. Other circuit configurations may, of course, also be chosen for the latches L in this case.
In order to allow the initialization with the two initialization signals bFPUP and FPUN, lines
13
are routed in the form of loops along the fuse banks
5
to
12
. FIG.
4
. shows one of the lines
13
, in the form of dashed lines, for the first initialization signal bFPUP. A corresponding line loop is required for the second initialization signal FPUN.
The first initialization signal bFPUP thus first of all runs on the line
13
along the fuse bank
5
from the center of the memory to its edge, and then along this fuse bank
5
back again, in order then to be routed successively in a corresponding manner through the fuse banks
6
to
12
.
Since the same situation also applies to the second initialization signal FPUN and to its line, this means that a total of four lines are in each case required along the fuse banks
5
to
12
and along mutually adjacent sides of the quadrants Q
1
to Q
4
.
Thus, in a corresponding way to the scheme shown in
FIG. 4
, the fuse initialization process runs sequentially over the entire chip of the memory, which results in a uniform current distributed over time, which is advantageous for starting up, during the initialization phase.
Depending on the chip architecture of a memory, the area consumed by individual areas on the chip may be dominated by transistors or by lines. In the latter case, a saving of lines reduces the area, which is a considerable advantage. This is particularly true when additional transistors are required due to the saving of lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for fuse initialization which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide a configuration for fuse initialization, in which it is possible to reduce the area that is required on a chip.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for fuse initialization, that includes: a plurality of latches; a plurality of fuse banks, each one of the plurality of the fuse banks having a plurality of fuses storing redundant information, each one of the plurality of the fuses associated with a respective one of the plurality of the latches; a generator device for generating a plurality of initialization signals which are used for reading the plurality of the fuses, the plurality of initialization signals including a first initialization signal and a second initialization signal; a plurality of first lines and a plurality of second lines; and a memory cell array having four quadrants, each o

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