Configuration for driving parallel lines in a memory cell config

Details Configuration for driving parallel lines in a memory cell config Configuration for driving parallel lines in a memory cell config

1999-06-17

2000-09-26

Dinh, Son T.

Static information storage and retrieval

Format or disposition of elements

365 63, 365174, 365182, G11C 502

Patent

active

061250503

ABSTRACT:
Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.

REFERENCES:
patent: 5311465 (1994-05-01), Mori et al.
patent: 5426605 (1995-06-01), Van Berkel et al.
patent: 5745407 (1998-04-01), Levy et al.

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