Configuration for crosstalk attenuation in word lines of DRAM ci

Details Configuration for crosstalk attenuation in word lines of DRAM ci Configuration for crosstalk attenuation in word lines of DRAM ci

1999-05-28

2000-12-12

Nelms, David

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

36518908, G11C 700

Patent

active

061607479

ABSTRACT:
A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.

REFERENCES:
patent: 3810124 (1974-05-01), Hoffman et al.
patent: 4602355 (1986-07-01), Watanabe
patent: 4764903 (1988-08-01), Siebert
patent: 5161121 (1992-11-01), Cho
patent: 5282167 (1994-01-01), Tanaka et al.

Affiliated with

Also associated with

Rating

Configuration for crosstalk attenuation in word lines of DRAM ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configuration for crosstalk attenuation in word lines of DRAM ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configuration for crosstalk attenuation in word lines of DRAM ci will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-223679