Patent
1996-01-31
1999-02-09
Teska, Kevin J.
G06F 9455, G06F 1750
Patent
active
058705864
ABSTRACT:
A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.
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"The Hardwire Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, 1994, pp. 2-23 through 2-25.
"The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, 1994, pp. 2-5 through 2-46.
"The XC5200 Logic Cell Array Family Technical Data Booklet" Oct. 1995 (referenced as XC5200.TM. FPGA Data Sheet) available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
"The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, 1994, pp. 2-7 through 2-46.
"The Programmable Logic Data Book", available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124, 1994, pp. 2-26.
Harms Jeanette S.
Mohamed Ayni
Richardson Kent
Teska Kevin J.
Xilinx , Inc.
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