Configuration bit read/write data shift register

Details Configuration bit read/write data shift register Configuration bit read/write data shift register

2000-04-01

2002-02-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000, C326S046000

Reexamination Certificate

active

06351139

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for reading and writing configuration bits for a programmable logic device generally and, more particularly, to a method and/or architecture for a configuration bit read/write data shift register.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) allows programmable logic to be implemented in an integrated circuit. Configuration bits are used to select the arrangement and operation of components within the PLD. In a static random access memory (SRAM) based PLD, the configuration bits are stored in a memory array.
The number of configuration bits can be very large. Programming the configuration bits in a parallel format would require a large number of pins that could be used for other purposes. A solution that would use a minimum number of pins to program configuration bits would be desirable.
In order to assure that a PLD is properly programmed, a solution that allows the configuration bits that are programmed into a programmable logic device to be verified would also be desirable.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate one or more first parallel data signals in response to a first serial data stream and a first control signal and (ii) generate a second serial data stream in response to one or more second parallel data signals and a second control signal. The second circuit may be configured to write the one or more first parallel data signals to and read the one or more second parallel data signals from an array of storage elements in response to one or more control signals.
The objects, features and advantages of the present invention include providing a method and/or architecture for a configuration bit read/write data shift register that may (i) use the same line and/or node for writing and reading data to a memory array, (ii) save one or more lines per shift register on circuit layouts, (iii) receive configuration bits in a serial data stream, (iv) generate a serial stream of configuration bits, (v) allow verification of configuration bits and/or (vi) shift data for one column of memory while writing another column of memory.


REFERENCES:
patent: 5787007 (1998-07-01), Bauer
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 5941974 (1999-08-01), Babin
patent: 6055594 (2000-04-01), Lo et al.

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