Configurable time borrowing flip-flops

Details Configurable time borrowing flip-flops Configurable time borrowing flip-flops

2011-01-11

2011-01-11

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S093000, C327S154000

Reexamination Certificate

active

07868655

ABSTRACT:
Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

REFERENCES:
patent: 5550782 (1996-08-01), Cliff et al.
patent: 6201415 (2001-03-01), Manglor
patent: 6608513 (2003-08-01), Tschanz et al.
patent: 6806739 (2004-10-01), Markovic et al.
patent: 6873187 (2005-03-01), Andrews et al.
patent: 6930522 (2005-08-01), Chang
patent: 7088136 (2006-08-01), Lewis
patent: 7107477 (2006-09-01), Singh et al.
patent: 7583103 (2009-09-01), Lewis et al.
patent: 2003/0001613 (2003-01-01), Nakaya
patent: 2005/0005214 (2005-01-01), Ueda
patent: 2005/0134348 (2005-06-01), Florescu
Boyle et al., U.S. Appl. No. 11/715,593, filed Mar. 7, 2007.
V. Stojanovic et al. “Comparative Anaysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems,” IEEE J. Solid State Circuits, vol. 34, No. 4, Apr. 1999, pp. 536-548.
N. Nedovic et al. “A Clock Skew Absorbing Flip-Flop,” 2003 IEEE International Solid State Circuits Conference, paper 19.5 (10 pages).
V.G. Oklobdzija, “Clocking and clocked storage elements in a multi-gigahertz environment”, IBM J. Res. & Dev. vol. 47 No. 5/6/ Sep./Nov. 2003, pp. 567-583.

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