Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-30
2001-08-21
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06279073
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of computer systems and more particularly to an improved configurable synchronizer for double data rate synchronous dynamic random access memory (DDR-SDRAM).
BACKGROUND OF THE INVENTION
A computer system is generally comprised of several component parts including a processor, random access memory, a data bus, and other peripheral devices and components. The processor accesses, modifies, and writes data to random access memory. The data contained in random access memory is transferred to the processor through the data bus. One type of random access memory is dynamic random access memory (DRAM). As computer processor speeds increase, faster random access memory is needed to fully realize the potential of faster processor chips. One solution for faster random access memory is synchronous DRAM (SDRAM). SDRAM is tied to a system clock and is designed to be able to read or write from memory in burst mode (after the initial read or write latency) at one clock cycle per access (zero wait states) at memory bus speeds up to 100 MHz. However, current computer processor speeds often exceed the capability of SDRAM to provide data from memory.
Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM) addresses the need for faster random access memory. DDR-SDRAM is similar in function to regular SDRAM, but it doubles the bandwidth of the memory by transferring data twice per cycle, on both the rising and falling edges of the clock signal. DDR-SDRAM returns a strobe signal synchronously with data signals. The strobe signal is related to the memory clock signal and indicates when valid data is ready for transfer from the DDR-SDRAM. Data signals are available on both the rising edge of the strobe signal and the falling edge of the strobe signal. Thus, two data signals are available with each clock cycle of a memory clock used for the DDR-SDRAM. In order to use DDR-SDRAM, the computer processor needs to synchronize the data coming from the DDR-SDRAM with the internal core clock of the computer processor chip. The internal core clock is often used to clock the data bus across which the data signals from the DDR-SDRAM are sent to the computer processor chip.
DDR-SDRAM may use a variety of DRAM configurations such as 4-bit DRAMs, 8-bit DRAMs, 16-bit DRAMs, or 32-bit DRAMs. Conventional synchronizers for DDR-SDRAM are usually designed for a single DDR-SDRAM configuration. Due to variations in DDR-SDRAM, the computer processor chip, and mother boards, strobe signals and data signals may not arrive together at the synchronizer. Conventional synchronizers for DDR-SDRAM are usually designed for a particular situation where the strobe signal and data signals do not arrive together. Therefore, it is desirable to provide a configurable synchronizer for DDR-SDRAM that allows the synchronizer to be optimized for various implementations.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a configurable synchronizer for DDR-SDRAM that provides improved flexibility and configurability. In accordance with the present invention, a configurable synchronizer for DDR-SDRAM is provided that substantially eliminates and reduces disadvantages and problems associated with conventional memory synchronizers.
According to an embodiment of the present invention, a configurable synchronizer for DDR-SDRAM is provided that includes a strobe select module operable to receive a memory select signal and to pass strobe signals from one or more DDR-SDRAMs to a number of synchronizer circuits corresponding to data signals passed in parallel by each DDR-SDRAM as indicated by the memory select signal. Each synchronizer circuit includes a rising edge latch for receiving a rising edge data signal from the DDR-SDRAM and to latch the rising edge data signal through the rising edge latch on a rising edge of the strobe signal. Each synchronizer circuit further includes a falling edge latch for receiving a falling edge data signal from the DDR-SDRAM and to latch the falling edge data signal through the falling edge latch on a falling edge of the strobe signal. Each synchronizer circuit further includes a data signal selector for receiving a data order control signal and to forward the rising edge data signal from the rising edge latch to an intermediate output on either a rising edge of a memory clock cycle or a falling edge of a memory clock cycle followed by forwarding the falling edge data signal from the falling edge latch to the intermediate output on an opposite edge of the memory clock cycle in response to the data order control signal. Each synchronizer circuit further includes an output latch operable to receive the intermediate output and to latch the intermediate output through the output latch to an output signal on each core clock cycle.
The present invention provides various technical advantages over conventional memory synchronizers. For example, one technical advantage is allowing various DDR-SDRAM configurations to be used with the configurable synchronizer. Another technical advantage is to provide several delay periods to delay a strobe signal so that it arrives with its associated data signals. Yet another technical advantage is to prevent false data signals from entering the configurable synchronizer by disabling the strobe signal after the last data signal is captured by the configurable synchronizer. A further technical advantage is in synchronization between the strobe signals and data signals from the DDR-SDRAM and a data bus clocked by an internal core clock with the synchronization window being movable in quarter cycle increments of a memory clock. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.
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Kim et al, “A 64-Mbit, 640-MByte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-MByte Memory System,” IEEE Journal of Solid-State Circuits, vol. 33, No. 11, pp. 1703-1710, Nov., 1998.*
International Search Report in International Application No. PCT/US 00/25296, dated Dec. 6, 2000, 7 pages.
McCall David L.
McCracken David E.
Baker & Botts L.L.P.
Elmore Stephen C.
Silicon Graphics Inc.
Thai Tuan V.
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