Configurable prioritization of core generated interrupts

Details Configurable prioritization of core generated interrupts Configurable prioritization of core generated interrupts

2001-10-12

2009-06-23

Cleary, Thomas J (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt prioritizing

C710S260000, C710S265000

Reexamination Certificate

active

07552261

ABSTRACT:
A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number of programmable interrupt priority level fields for storing priority levels for the core generated interrupts, and for the externally generated interrupts, if desired. The apparatus further includes a programmable offset register for storing an offset to be used in calculating the interrupt vector. The apparatus further includes a priority encoder that sorts all of the received interrupts, whether on-core or off-core, according to their priority, utilizing the programmed interrupt priority levels. The priority encoder provides an indication of the received interrupt with the highest priority to a vector generator. The vector generator receives the indication, and calculates an interrupt vector utilizing the programmed offset. Use of the priority encoder and vector generator allows a processing system to programmably specify how core generated interrupts are to be prioritized against external interrupts, thereby allowing interrupt vectors to be directly calculated for core generated interrupts.

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