Configurable pipe delay with window overlap for DDR receive...

Details Configurable pipe delay with window overlap for DDR receive... Configurable pipe delay with window overlap for DDR receive...

2005-09-27

2005-09-27

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S233500, C365S189050

Reexamination Certificate

active

06950350

ABSTRACT:
A system for maximizing set up and hold times for data reads from a DDR memory device. The system adjusts timing of a strobe from a DDR memory device and converts data from the DDR memory device into a single-data-rate data. The timing adjustment is preferably controlled through software, and the system selectively determines if an extra half cycle should be added to the data path to optimize data reads.

REFERENCES:
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patent: 6016283 (2000-01-01), Jeong
patent: 6044032 (2000-03-01), Li
patent: 6060916 (2000-05-01), Park
patent: 6061292 (2000-05-01), Gray et al.
patent: 6134182 (2000-10-01), Pilo et al.
patent: 6154419 (2000-11-01), Shakkarwar
patent: 6279073 (2001-08-01), McCracken et al.
patent: 6381194 (2002-04-01), Li

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