Configurable performance-optimized programmable logic device

Details Configurable performance-optimized programmable logic device Configurable performance-optimized programmable logic device

1996-04-11

1998-09-01

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 33, 326 81, 326 86, H03K 190185

Patent

active

058015485

ABSTRACT:
A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

REFERENCES:
patent: 4585955 (1986-04-01), Uchida
patent: 5402387 (1995-03-01), Hotta
patent: 5408147 (1995-04-01), Yarbrough et al.
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5612637 (1997-03-01), Shay et al.
Xilinx, Inc., The Programmable Logic Data Book, 1994, Section 3, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.

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