Configurable on-die termination

Details Configurable on-die termination Configurable on-die termination

2005-12-19

2008-10-21

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000

Reexamination Certificate

active

07439760

ABSTRACT:
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

REFERENCES:
patent: 5254883 (1993-10-01), Horowitz
patent: 5298800 (1994-03-01), Dunlop
patent: 5396028 (1995-03-01), Tomassetti
patent: 5467455 (1995-11-01), Gay
patent: 5663661 (1997-09-01), Dillon
patent: 5666078 (1997-09-01), Lamphier
patent: 5680060 (1997-10-01), Banniza
patent: 5726582 (1998-03-01), Hedberg
patent: 5781028 (1998-07-01), Decuir
patent: 5926031 (1999-07-01), Wallace
patent: 5969658 (1999-10-01), Naylor
patent: 5982191 (1999-11-01), Starr
patent: 5995894 (1999-11-01), Wendte
patent: 6028484 (2000-02-01), Cole
patent: 6060907 (2000-05-01), Vishwanthaiah et al.
patent: 6064224 (2000-05-01), Esch, Jr.
patent: 6157206 (2000-12-01), Taylor
patent: 6232792 (2001-05-01), Starr
patent: 6266001 (2001-07-01), Fang
patent: 6288564 (2001-09-01), Hedberg
patent: 6308232 (2001-10-01), Gasbarro
patent: 6344765 (2002-02-01), Taguchi
patent: 6353334 (2002-03-01), Schultz et al.
patent: 6356105 (2002-03-01), Volk
patent: 6356106 (2002-03-01), Greef
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6411122 (2002-06-01), Mughal
patent: 6418500 (2002-07-01), Gai
patent: 6424170 (2002-07-01), Raman
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6462588 (2002-10-01), Lau
patent: 6462591 (2002-10-01), Garrett, Jr.
patent: 6495997 (2002-12-01), Hall
patent: 6509756 (2003-01-01), Yu
patent: 6525558 (2003-02-01), Kim
patent: 6530062 (2003-03-01), Liaw et al.
patent: 6545522 (2003-04-01), Mughal
patent: 6552565 (2003-04-01), Chang
patent: 6573746 (2003-06-01), Kim
patent: 6573747 (2003-06-01), Radhakrishnan
patent: 6608507 (2003-08-01), Garrett, Jr.
patent: 6661250 (2003-12-01), Kim
patent: 6711073 (2004-03-01), Martin
patent: 6734702 (2004-05-01), Ikeoku
patent: 6762620 (2004-07-01), Jang
patent: 6768352 (2004-07-01), Maher
patent: 6781405 (2004-08-01), Rajan et al.
patent: 6806728 (2004-10-01), Nguyen
patent: 6856169 (2005-02-01), Frans
patent: 6894691 (2005-05-01), Juenger
patent: 6924660 (2005-08-01), Nguyen
patent: 6940303 (2005-09-01), Vargas
patent: 6965529 (2005-11-01), Zumkeher
patent: 6980020 (2005-12-01), Best
patent: 7038498 (2006-05-01), Funaba
patent: 7102200 (2006-09-01), Fan
patent: 7102390 (2006-09-01), Frans et al.
patent: 7123047 (2006-10-01), Lim
patent: 7135884 (2006-11-01), Talbot et al.
patent: 7148721 (2006-12-01), Park
patent: 7196567 (2007-03-01), Nguyen
patent: 7245154 (2007-07-01), Davidson et al.
patent: 7268712 (2007-09-01), Sheen
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 2003/0112751 (2003-06-01), Yuffe
patent: 2004/0124850 (2004-07-01), Koneru
patent: 2004/0201402 (2004-10-01), Rajan
patent: 2005/0057275 (2005-03-01), Nguyen
patent: 2005/0225353 (2005-10-01), Kwon
patent: 2006/0007761 (2006-01-01), Ware
patent: 2006/0071683 (2006-04-01), Best
patent: 2006/0077731 (2006-04-01), Ware
patent: 2007/0007992 (2007-01-01), Bains
patent: 2007/0070717 (2007-03-01), Kim
patent: 0 817 441 (1998-01-01), None
patent: 02140676 (1990-05-01), None
patent: 2005/119471 (2005-12-01), None
patent: WO 97/02658 (1997-01-01), None
patent: WO 98/04041 (1998-01-01), None
patent: WO 00/41300 (2000-07-01), None
patent: WO 00/70474 (2000-11-01), None
patent: WO 2004/061690 (2004-07-01), None
Johnson, Chris. “The Future of Memory: Graphics DDR3 SDRAM Functionality.” Micron Designline, vol. 11, Issue 4, 4Q02. 8 pages.
Johnson, Chris, “Graphics DDR3 On-Die Termination and Thermal Considerations.” Micron Designline, vol. 12, Issue 1. Rev. Apr. 1, 2003. 1Q03/2Q03. 8 pages.
Farrell, Todd, “Core Architecture Doubles MEM Data Rate,” in Electronic Engineering Times Asia, Dec. 16, 2005. 4 pages.
Janzen, Jeff, “DDR2 Offers New Features and Functionality,” Designline, vol. 12, Issue 2, Micron, 16 pages, Jul. 31, 2003 EN.L.
Weidlich, Rainer, “What comes Next in Commodity DRAMS—DDR3,” Infineon Technologies, Jun. 2005, 4 pages.
Hynix and DDR3, Keynote Address at JEDEX Shanghai 2005, Oct. 2005, 24 pages.
Micron Technical Note, “DDR2-533 Memory Design Guide for Two-DIMM Unbuffered Systems,” TN-47-01, 2003, 19 pages.
Lee, D.Y. and Rhoden, Desi, “DDR/DDR2/DDR3 Tutorial,” Samsung and Inphi, JEDEX San Jose, 2005, 130 pages.
Roden, Desi “The Evolution of DDR,” Via Technology Forum 2005, Inphi Corp., 23 pages. drhoden@inphi-copr.com.
Shen, Dr. William Wu, “DDR3 Functional Outlook,” Infineon, JEDEX Shanghai, Oct. 25-26, 2005, 30 pages.
Lee, K.H., “MultimediaCard Solutions of Digital Storage Applications,” Samsung Electronics, JEDEX Shanghai, Oct. 25-26, 2005, 28 pages.
Gervasi, Bill “DRAM Module Market Overview,” SimpleTech, JEDEX Shanghai, Oct. 25-26, 2005, 50 pages.
Trost, Hans-Peter “Press Presentation DDR3 Introduction,” Memory Products Group, Infineon Technologies, AG, Jun. 2005, 11 pages.
Micron Technical Note, TN-47-07: DDR2 Simulation Support; Rev A Jul. 2005.
DDR2 ODT Control; Product Planning & Application Engineering Team, Dec. 2004, pp. 8.
Cao, T et al. “On-Chip Programmable Termination Scheme.” IP.Com PriorArtDatabase—Technical Disclosure. Original publication date Feb. 1, 1995. 4 pages.
“LVDS Multidrop Connections, Application Report, Mixed Signal Products (SLLA054).” Copyright Texas Instruments. Jul. 1999. 37 pages.
Black, Mike, “Xilinx/Micron Partner to Provide High-Speed Memory Interfaces.” Xcell Journal, First Quarter 2005. 2 pages.
“Low-Voltage Differential Signaling.” Copyright The International Engineering Consortium. Downloaded from Web ProForum Tutorials http://www.ied.org. 15 pages. Dec. 2005.
“Achieving Flexible, High Performance I/O with RapidChip Platform ASICs.” Copyright LSI Logic Corporation. 2005. 7 pages.
Huq, Syed B. et al., “An Overview of LVDS Technology.” 1998 National Semiconductor Corporation. 12 pages.
Khouri, Gaby “Evaluation of Alcatel Patent Portfolio by Semiconductor Insights.” Nov. 2004. Copyright Semiconductor Insights Inc. 38 pages.
Knight, Thomas F. Jr., “A Self-Terminating Low-Voltage Swing CMOS Output Driver.” IEEE Journal of Solid-State Circuits, vol. 23, No. 2, Apr. 1988, pp. 457-464.
Gabara, Thaddeus J., “On-Chip Terminating Resistors for High Speed ECL-CMOS Interfaces.” Feb. 1992. IEEE. pp. 292-295.
Micron, “Graphics DDR3 DRAM.” Advance. “256 Mb × 32 GDR3 DRAM.” © 2003 Micron Technology, Inc. pp. 1-67.
Kim, Su-Chul, “Programmable Digital On-Chip Terminator.” ITC-CSCC, 2002. 4 pages.

Affiliated with

Also associated with

Rating

Configurable on-die termination does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable on-die termination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable on-die termination will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4007504