Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-12-30
2002-05-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S047000
Reexamination Certificate
active
06388464
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices generally and, more particularly, to a configurable memory for programmable logic devices.
BACKGROUND OF THE INVENTION
Traditionally there are two types of programmable logic architectures: complex programmable logic device (CPLDs) and field programmable gate arrays (FPGAs). The CPLD can be constructed as a one-dimensional array of logic blocks made of 16 macrocells and a product term array connected through a single central interconnect scheme. The CPLD achieves high performance by being able to complete a complex logic function in a single pass of the logic array, and has predictable timing by having every output or I/O pin connected to every logic block input through a central interconnect structure. The CPLD can be non-volatile by using an EEPROM process. However, the CPLD has no available on-chip RAM.
An FPGA architecture is constructed from a two dimensional array of logic blocks called CLBs. The CLBs are made from 4-input look-up-tables (LUTs) and flip-flops. The LUTs can be used as distributed memory blocks. The CLBs are connected by a segmented interconnect structure. The FPGA architecture supports a low standby power and the LUTs can use a simple logic CMOS process. Since the two-dimensional array of CLBs and the segmented interconnect structure are scalable, an FPGA can achieve high density. However, a dual port or FIFO memory is slow and inefficient to implement with LUTs.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
The objects, features and advantages of the present invention include providing an architecture, circuit and/or method for a configurable memory that may (i) provide a configurable single port RAM, dual port RAM and/or FIFO, (ii) provide dedicated dual port memory logic and arbitration, and FIFO memory logic and flags that may improve memory performance, (iii) be placed in the routing channels of a programmable logic device to achieve higher performance with I/O blocks, (iv) be cascadable with other configurable memory blocks to form larger block sizes and/or (v) be used as synchronous or asynchronous memory.
REFERENCES:
patent: 4878200 (1989-10-01), Asghar et al.
patent: 5136188 (1992-08-01), Ha et al.
patent: 5144582 (1992-09-01), Steele
patent: 5280202 (1994-01-01), Chan et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5422823 (1995-06-01), Agrawal et al.
patent: 5451887 (1995-09-01), El-Avat et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5521529 (1996-05-01), Agrawal et al.
patent: 5537057 (1996-07-01), Leong et al.
patent: 5587945 (1996-12-01), Lin et al.
patent: 5646901 (1997-07-01), Sharpe-Geisler et al.
patent: 5781030 (1998-07-01), Agrawal et al.
patent: 5799176 (1998-08-01), Kapusta et al.
patent: 5811987 (1998-09-01), Ashmore et al.
patent: 5818254 (1998-10-01), Agrawal et al.
patent: 5848285 (1998-12-01), Kapusta et al.
patent: 5966027 (1999-10-01), Kapusta et al.
patent: 5977791 (1999-11-01), Veenstra
patent: 6049223 (2000-04-01), Lytle et al.
patent: 6058452 (2000-05-01), Rangasayee et al.
patent: 6134181 (2000-10-01), Landry
patent: 6137308 (2000-10-01), Nayak
patent: 6191998 (2001-02-01), Reddy et al.
patent: 6201407 (2001-03-01), Kapusta et al.
“Hybrid Product Term and Lut Based Architectures Using Embedded Memory Blocks”, By Frank Heile and Andrew Leaver, pp. 13-16.
“An Innovative, Segmented High Performance FPGA Family With Variable-Grain-Architecture and Wide-Gating Functions”, By Om Agrawal et al., pp. 17-26.
“A New High Density And Very Low Cost Reprogrammable FPGA Architecture”, By Sinan Kaptanoglu et al., pp. 3-12.
“XC4000E and XC4000X Series Field Programmable Gate Arrays”, XILINX, May 14, 1996 (Version 1.6), pp. 6-5 to 6-72.
“XC4000XLA/XV Field Programmable Gate Arrays”, XILINX, Oct. 18, 1999, pp. 6-157 to 6-170.
“Virtex ™ 2.5V Field Programmable Gate Arrays”, XILINX, Apr. 2, 2001, pp. 1-20.
“Coolrunner ® XPLA3 CPLD”, Xilinx, Apr. 11, 2001, pp. 1-10.
“Spartan And Spartan-XL Families Field Programmable Gate Arrays”, Xilinx, Mar. 2, 2000, pp. 4-1 to 4-66.
“XC9500XV Family High-Perfromance CPLD”,Xilinx, Jan. 15, 2001, pp. 1-18.
“Integrated Product-Term Logic In Apex 20K Devices”, Altera, Apr. 1999, ver. 1.0, pp. 1-12.
“Apex II Programmable Logic Device Family”, Altera, May 2001, ver. 1.1, pp. 1-96.
“Flex 8000 Programmable Logic Device Family”, Altera, Jun. 1999, ver. 10.01, pp. 349-410.
“Flex 10K Embedded Programmable Logic Device Family”, Altera, Mar. 2001, ver. 4.1, pp. 1-128.
“Max 7000 Programmable Logic Device Family”, Altera, Mar. 2001, ver. 6.1, pp. 1-62.
“Max 9000 Programmable Logic Device Family”, Altera, Jul. 1999, ver. 6.01, pp. 1-40.
“Mach 5 CPLD Family—Fifth Generation Mach Architecture”, Lattice Semiconductor Corp., Rev. 1, Sep. 2000, p. 1-47.
Timothy M. Lacey et al., “Programmable Logic Device”, U.S. Serial No. 09/475,879, Filed Dec. 30, 1999.
Johnson David L.
Lacey Timothy M.
Cho James H.
Cypress Semiconductor Corp.
Malorana, P.C. Christopher P.
Miller Robert M.
Tokar Michael
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