Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2002-04-26
2003-12-30
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S039000, C326S041000
Reexamination Certificate
active
06670826
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to configurable logic blocks in programmable logic devices. More particularly, the invention relates to a configurable logic block including a storage element clocked by a write strobe pulse.
FIELD THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1
is a simplified block diagram of a portion of a typical CLB. This structure is included, for example, in the CLBs of the Virtex™ FPGAs available from Xilinx, Inc. The Virtex CLB is described in pages 3-79 through 3-82 of “The Programmable Logic Data Book 2000”, published April, 2000 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
As shown in
FIG. 1
, a typical CLB includes a function generator FG having n data input signals F(
1
:n). Function generator FG is often implemented, for example, as a 4-input lookup table (where n=4) containing data stored in configuration memory cells for the PLD. Thus, the lookup table provides any function of up to
4
inputs at output terminal FCN.
In advanced FPGAs such as the Virtex FPGA, the function generator can also be programmed to function as a RAM. To provide this capability, a write strobe generator WSG is also included in the CLB. Write strobe generator WSG accepts an input clock signal CK and provides a HOLD signal and a write strobe signal WS to function generator FG. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
For example, in response to a rising edge on input clock signal CK, write strobe generator WSG drives signals HOLD and WS high, waits a sufficient time to accomplish a write to the function generator in RAM mode, brings write strobe signal WS low again, and finally brings the HOLD signal low. The HOLD signal must remain high after write strobe signal WS goes low, to prevent changes on the data input signals F(
1
:n) from reaching the RAM while write strobe signal WS is still active.
The typical CLB of
FIG. 1
also includes another element, flip-flop FF. Flip-flop FF is a storage element that can be optionally included in the output path of the CLB. Flip-flop FF typically uses the same clock signal CK that drives write strobe generator WSG. The data input terminal IN of flip-flop FF is driven by the output signal FCN of function generator FG. The CLB output can be taken either from the flip-flop output XQ or directly from the FCN output terminal of function generator FG. Additional programmable data paths and elements are also commonly included in a CLB. These data paths and elements are not shown in
FIG. 1
, for clarity, but are well known in the art of PLD design.
FIG. 2
shows one implementation of flip-flop FF that is compatible with the CLB of FIG.
1
. The flip-flop of
FIG. 2
includes two latches (L
1
, L
2
), each including two cross-coupled inverters (
203
and
204
,
206
and
207
, respectively). Data input signal IN is passed to latch L
1
through passgate
202
when clock signal CK goes low. The data value from latch L
1
is then passed to latch L
2
through passgate
205
when clock signal CK goes high. Thus, in the flip-flop of FIG.
2
and given a change in the state of data input signal IN, the signal stored in latch L
2
(D) changes state the next time clock signal CK changes from low to high.
Note that latched data signal D is twice inverted from data input signal IN, and thus has the same sense as that signal. Similarly, output signal OUT is twice inverted from latched data signal D (through inverters
208
and
209
), and therefore also has the same sense as data input signal IN. Inverted latched data signal DB and inverted output signal OUTB have the opposite sense from data input signal IN.
There are many well-known variations on the flip-flop of FIG.
2
. For example, an active-high reset signal can be added by replacing inverters
203
and
207
with
2
-input NOR gates, of which the second input is the active-high reset signal. (When the reset signal goes high, the NOR output signals are forced low.) Similarly, an active-high set signal can be added by replacing inverters
204
and
206
with 2-input NOR gates, of which the second input is the active-high set signal. Active-low set and reset signals can be added by substituting 2-input NAND gates, rather than NOR gates, for the alternative inverters in each latch.
Another desirable variation involves the addition of initialization circuitry. An initialization circuit can cause the flip-flop to assume a predetermined state on receipt of an initialization signal. For example, the initialization can be performed by utilizing the set and reset circuitry previously described.
For initialization circuitry as well as with set and reset circuits, the desired result must be applied to both latches. If applied only to the first latch (e.g., L
1
), the output of the flip-flop is not initialized unless the clock signal CK is high. If applied only to the second latch (e.g., L
2
), the flip-flop only stays initialized as long as clock signal CK is low.
There are inherent drawbacks to the flip-flop of FIG.
2
. One drawback is that it can be difficult to “trip” a latch while writing a new value to only one of the two nodes of the latch, particularly if passgate
202
is implemented as an N-channel transistor rather than a CMOS passgate. For example, to pass a new value to latch L
1
of
FIG. 2
(i.e., to place the new value on the output of inverter
203
), the new value must overwrite an opposing value provided by the inverter. Therefore, careful circuit design is often required to successfully implement the circuit. This drawback can be overcome by placing another passgate on the feedback path (e.g., on the output of inverter
203
), clocked by the inverse of the signals used to clock passgate
202
. However, the addition of the new passgate for each of two latches increases the size of the flip-flop.
Another drawback to the flip-flop of
FIG. 2
is not so easily overcome. The circuit is subject to several race conditions. Referring again to
FIG. 2
, for the circuit to function properly passgate
205
must turn off before passgate
202
turns on. However, passgate
202
should also turn off as soon as possible, to minimize the hold time of the circuit. If feedback passgates are used to make it easier to trip the latches, as described above, these passgates are also subject to race conditions.
While not a simple task, circuitry can be designed that achieves the desired result by ensuring that the correct clock signal wins the race in each instance. However, alterations to the circuit or to the circuit layout, or even to the fabrication process used to manufacture the device, can cause the race conditions to reappear and the modified flip-flop to malfunction.
This condition worsens as additional functionality is added to the flip-flop. The addition of set and/or reset circuitry and initialization capability can significantly alter the “race”, compounding the problems described above.
FIG. 3
shows a second well-known flip-flop that is widely used in CLBs such as that shown in FIG.
1
Cartier Lois D.
Tran Anh
Xilinx , Inc.
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