Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-04
2003-05-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06567969
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to programmable logic devices and, more particularly, to programmable gate arrays consisting of an array of logic blocks and input/output blocks with an interconnection structure, each of which are configurable by a configuration program stored in on chip memory.
DESCRIPTION OF RELATED ART
The programmable gate array is a high performance, user programmable device containing three types of configurable elements that are customized to a user system design. The three elements are (1) an array of configurable logic blocks (CLBs), (2) with input/output blocks (IOBs) around a perimeter, all linked by (3) a flexible programmable interconnect network.
The system design desired by a user is implemented in the device by configuring programmable RAM cells. These RAM cells control the logic functionality performed by the CLBs, IOBs and the interconnect. The configuration is implemented using PGA design software tools.
It is generally accepted that the programmable gate array was first commercially introduced by Xilinx of San Jose, Calif. Xilinx originally introduced the XC2000 series of logic cell arrays and has more recently introduced a second generation XC3000 family of integrated circuit programmable gate arrays. A description of the 2000 series, as well as related programmable logic device art, can be found in THE PROGRAMMABLE GATE ARRAY DESIGN HANDBOOK, First Edition, published by Xilinx, pages 1-1 through 1-31. The architecture for the XC3000 family is provided in a technical data handbook published by Xilinx entitled XC3000 LOGIC CELL ARRAY FAMILY, pages 1-31. Each of these Xilinx publications is incorporated by reference in this application as providing a description of the prior art.
The prior art in programmable gate arrays is further exemplified by U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is assigned to Xilinx, Inc. These U.S. Patents are incorporated by reference as setting forth detailed descriptions of the programmable gate array architecture and implementations of the same.
As mentioned above, the programmable gate array consists of a configurable interconnect, a ring of configurable input/output blocks, and an array of configurable logic blocks. It is the combination of these three major features that provides flexibility and data processing power for programmable gate arrays. However, the programmable gate arrays of the prior art suffer certain limitations in each of the interconnect structure, the input/output block structures, and the configurable logic block structures.
The configurable interconnect structure must provide the ability to form networks on the programmable gate array which optimize utilization of the resources on the chip. The prior art interconnect systems have tended to force connection in the logical network to configurable blocks in a relatively small area. For instance, a prior system provides direct connections only between adjacent configurable logic blocks. The inputs and outputs on the configurable logic blocks are arranged in a left to right or otherwise asymmetrical layout that forces signal flow in a certain direction across the chip. This causes congestion on the interconnect structure for applications requiring a large number of inputs or outputs. Also, this forces the printed circuit board layout, which includes one of these asymmetrically designed logic cell arrays, to provide for inputs on one side of the logic cell array and outputs on the other.
In addition, the prior art interconnect structures are limited in the number of multi-source networks that can be implemented.
The input/output blocks in the prior art programmable gate arrays are relatively complex macro cells in order to provide flexibility needed for the wide variety of applications intended for the devices. However, these complex macro cells include resources that are unused in many configurations of the input/output blocks. Further, the blocks are relatively slow because of the complexity, requiring passage through a number of buffers, multiplexers and registers between the logic cells and the input/output pad. Furthermore, the input/output blocks cause congestion on the peripheral logic blocks in the device for applications involving a lot of input and output.
The configurable logic blocks themselves also suffer limitations which impact the flexibility of the device. The logic blocks of the prior art have operated upon a relatively small set of input variables. Thus, wide gating functions, such as decoding a 16 bit instruction or a wide multiplexing function, required cascading of many configurable blocks. Thus, a very simple function can utilize a large number of configurable logic blocks in the array. Further, when cascading blocks, due to the limitation of the number of direct interconnections between the logic blocks, many of the signals have to be transmitted across the programmable general connect. This causes delay because of the number of programmable interconnection points used. Further, for critical paths requiring fast operation, the cascading of blocks becomes impractical.
In the prior art configurable logic blocks, typically four input signals are used for the logic function. In order to obtain a five variable gating function, the configurable logic blocks used a sharing of inputs scheme. This sharing of inputs greatly limits the logic flexibility for these five variable functions in the prior art.
Prior art configurable logic blocks also suffered speed penalties because of the relatively complex structure required for the blocks to achieve user flexibility. For a block which is being used for a simple function, the logic would be propagated at a relatively slow rate because of the complex structures required.
It is desirable to provide a programmable gate array which provides for greater flexibility and logic power than provided by prior art devices.
SUMMARY OF THE INVENTION
The present invention provides an architecture for a configurable logic array with an interconnect structure which improves flexibility in creating networks to allow for greater utilization of the configurable logic blocks and input/output blocks on the device.
Accordingly, the present invention is an improved configurable logic array comprising a configuration memory storing program data specifying a user defined data processing function. In addition, a plurality of configurable logic blocks are arranged in an array consisting of C columns and R rows. Each configurable logic block is coupled to the configuration memory and has a plurality of inputs and outputs for generating output signals at the respective outputs in response to the input signals at the respective inputs and in response to program data in the configuration store. A plurality of configurable input/output blocks is included, each coupled to an input/output pad and to the configuration store, and having at least one input and at least one output. The configurable input/output blocks provide configurable interfaces between the respective pads and the respective inputs and outputs in response to the program data. A configurable interconnect is coupled to the configurable logic blocks, configurable input/output blocks and to the configuration store, for connecting the inputs and outputs of configurable logic blocks and configurable input/output blocks into logical networks in response to the program data in the configuration store.
According to one aspect of the invention, the configurable interconnect is symmetrically disposed relative to the inputs and outputs of the configurable logic blocks. Thus, inputs of the CLBs can be derived from four sides and outputs can be driven to four sides of the respective CLB into a symmetrical interconnect structure.
The interconnect includes a plurality of horizontal buses along the rows of CLBs and a plurality of vertical buses along the columns of CLBs. The intersections of the horizontal and vertical buses are configurable to route networks across the device.
Another aspect of the inte
Agrawal Om Prakash
Shen Ju
Wright Michael James
Do Thuan
Gimlan Gideon
Lattice Semiconductor Corporation
MacPherson Kwok & Chen & Heid LLP
Smith Matthew
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