Configurable integrated circuit with offset connection

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S047000, C326S101000

Reexamination Certificate

active

10882713

ABSTRACT:
Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6326651 (2001-12-01), Manabe
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6992505 (2006-01-01), Zhou
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0196056 (2004-10-01), Ting
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.
Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, slides 1-74, Synopsys, Inc., no month.
U.S. Appl. No. 10/882,945, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,848, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/883,502, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,945, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,945, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,848, filed Jun. 30, 2004, Rohe.
“§3 Programmable Logic Devices,”Digital System Design, 2001, pp. 3.1-3.28, no month.
“The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, pp. 1-10, no date.
“The Xilinx Virtex Series FPGA,” Jan. 22, 2001, slides 1-22.
“Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,”ISCA'04, 2004, ACM, Munchen, Oberbayern, Germany, no month.
Agrawal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions,”FPGA99,1999, pp. 17-26, ACM, Monterey, CA, USA, no month.
Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,”FPGA2000, 2000, ACM, Monterey, CA, USA, no month.
Altera Corp., “6 DSP Blocks in Stratix II Devices,”SII52006-1.0, Feb. 2004, pp. 1-32.
ALTERA, “Stratix II DSP Performance,”White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.
Backus, J., “Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs,”Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, no. 8, ACM.
Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set,”A Technology Application Whitepaper, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, no month.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 487-494, IEEE, no month.
Caspi, E., et al., “A Streaming Multi-Threaded Model,”MSP-3, Dec. 2, 2001, pp. 1-23.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Executiion (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Compton, K., et al., “An Introduction to Reconfigurable Computing,” no month.
Compton, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY.
Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc.
Davare, A., et al., “The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications,”DAC'04, Jun. 7-11, 2004, ACM, San Diego, California, USA.
Dehon, A., Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization). pp. 1-10. (Applicants believe that this article also appears inProceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134.)
Dehon, A., “DPGA Utilization and Application,” no date.
Dehon, A., “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,”Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54.
Dehon, A., “Reconfigurable Architectures for General-Purpose Computing,” A.I. Technical Report No. 1586, Oct. 1996, pp. i-353.
Dehon, A., “The Density Advantage of Configurable Computing,” Apr. 2000, pp. 41-49; IEEE.
Dehon, A., “Transit Note #121: Notes on Programmable Interconnect,”M.I.T. Transit Project, Feb. 1995, pp. 1-13.
Dehon, A., et al., “Design Patterns for Reconfigurable Computing,”Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 2004.
Dehon, A., et al., “DPGA-Coupled Microprocessors: Commodi

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Configurable integrated circuit with offset connection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable integrated circuit with offset connection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable integrated circuit with offset connection will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3724120

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.