Configurable integrated circuit with built-in turns

Details Configurable integrated circuit with built-in turns Configurable integrated circuit with built-in turns

2007-12-25

2007-12-25

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S039000, C326S040000, C326S041000, C326S047000, C716S030000

Reexamination Certificate

active

10882945

ABSTRACT:
Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the same row. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by a set of wire segments that traverse through a set of the IC's wiring layers, and a set of vias when multiple wiring layers are involved. Some of the direct connections may have intervening circuits (e.g. buffer circuits). In some embodiments, the nodes in the array are all similar to each other.

REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6233191 (2001-05-01), Gould et al.
patent: 6275064 (2001-08-01), Agrawal et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6326651 (2001-12-01), Manabe
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6496918 (2002-12-01), DeHon et al.
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6992505 (2006-01-01), Zhou
patent: 7126372 (2006-10-01), Vadi et al.
patent: 7129746 (2006-10-01), Balasubramanian et al.
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0196066 (2004-10-01), Ting
U.S. Appl. No. 10/882,713, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,848, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/883,502, filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,713 (Non-Final Rejection), filed Jun. 30, 2004, Rohe.
U.S. Appl. No. 10/882,848 (Non-Final Rejection), filed Jun. 30, 2004, Rohe.
“§3 Programmable Logic Devices,”Digital System Design, 2001, pp. 3.1-3.28. Month N/A.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation.
“The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, pp. 1-10. Date N/A.
“The Xilinx Virtex Series FPGA,” Jan. 22, 2001, slides 1-22.
“Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,”ISCA '04, 2004, ACM, Munchen, Oberbayern, Germany, Month N/A.
Agarwal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions,”FPGA 99, 1999, pp. 17-26, ACM, Monterey, CA, USA.
Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,”FPGA 2000, 2000, ACM, Monterey, CA, USA.
Altera Corp., “6. DSP Blocks in Stratix II Devices,”SII52006-1.0, Feb. 2004, pp. 1-32.
Altera, “Stratix II DSP Performance,”White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.
Backus, J., “Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs,”Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM.
Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set,”A Technology Application Whitepaper, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, Month N/A.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 487-494, IEEE, Month N/A.
Camposano, R., “The Growing Semiconductor Zoo: ASCIs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, pp. 1-74, Synopsys, Inc.
Caspi, E., et al., “A Streaming Multi-Threaded Model,”MSP-3, Dec. 2, 2001, pp. 1-23.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Executiion (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Compton, K., et al., “An Introduction to Reconfigurable Computing,”, date N/A.
Compton, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, NY.
Cong, J., et al., “Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,”ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc.
Davare, A., et al., “The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications,”DAC '04, Jun. 7-11, 2004, ACM, San Diego, California, USA.
Dehon, A., Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization). pp. 1-10. (Applicants believe that this article also appears inProceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134.).
Dehon, A., “DPGA Utilization and Application.” Feb. 11-13, 1996.
Dehon, A., “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,”Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54.
Dehon, A., “Reconfigurable Architectures for General-Purpose Computing,”A.I.

Affiliated with

Also associated with

Rating

Configurable integrated circuit with built-in turns does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable integrated circuit with built-in turns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable integrated circuit with built-in turns will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3868543