Electronic digital logic circuitry – Reliability
Reexamination Certificate
2006-03-13
2009-06-23
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S014000, C326S016000, C326S038000
Reexamination Certificate
active
07550991
ABSTRACT:
Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC further includes a trace buffer for storing user-design state values associated with an operational trigger even of the IC. In some embodiments, the configurable circuits, UDS circuits, and tracer buffer are on a single IC die.
REFERENCES:
patent: 5425036 (1995-06-01), Liu et al.
patent: 5426378 (1995-06-01), Ong
patent: 5452239 (1995-09-01), Dai et al.
patent: 5521835 (1996-05-01), Trimberger
patent: 5600263 (1997-02-01), Trimberger et al.
patent: 5610829 (1997-03-01), Trimberger
patent: 5629637 (1997-05-01), Trimberger et al.
patent: 5640106 (1997-06-01), Erickson et al.
patent: 5640107 (1997-06-01), Kruse
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5654650 (1997-08-01), Gissel
patent: 5701441 (1997-12-01), Trimberger
patent: 5761483 (1998-06-01), Trimberger
patent: 5825662 (1998-10-01), Trimberger
patent: 5920712 (1999-07-01), Kuijsten
patent: 5944813 (1999-08-01), Trimberger
patent: 6084429 (2000-07-01), Trimberger
patent: 6182247 (2001-01-01), Herrmann et al.
patent: 6255849 (2001-07-01), Mohan
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6404224 (2002-06-01), Azegami et al.
patent: 6430736 (2002-08-01), Levi et al.
patent: 6446249 (2002-09-01), Wang et al.
patent: 6460148 (2002-10-01), Veenstra et al.
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6614703 (2003-09-01), Pitts et al.
patent: 6668237 (2003-12-01), Guccione et al.
patent: 6681353 (2004-01-01), Barrow
patent: 6704889 (2004-03-01), Veenstra et al.
patent: 6802026 (2004-10-01), Patterson et al.
patent: 6810442 (2004-10-01), Lin et al.
patent: 6829756 (2004-12-01), Trimberger
patent: 6889368 (2005-05-01), Mark et al.
patent: 6894527 (2005-05-01), Donlin et al.
patent: 7010667 (2006-03-01), Vorbach et al.
patent: 7064577 (2006-06-01), Lee
patent: 7085858 (2006-08-01), Fox et al.
patent: 7112992 (2006-09-01), Guzman et al.
patent: 7138827 (2006-11-01), Trimberger
patent: 7212448 (2007-05-01), Trimberger
patent: 7231339 (2007-06-01), Nemecek et al.
patent: 7233169 (2007-06-01), Vadi
patent: 7375550 (2008-05-01), Redgrave et al.
patent: 7443196 (2008-10-01), Redgrave et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2002/0089349 (2002-07-01), Barbier et al.
patent: 2003/0100133 (2003-05-01), Eidson et al.
patent: 2006/0176075 (2006-08-01), Or-Bach
patent: 2006/0251416 (2006-11-01), Letner et al.
patent: 2007/0007999 (2007-01-01), Graham et al.
patent: 2007/0143577 (2007-06-01), Smith
patent: 2008/0191735 (2008-08-01), Redgrave et al.
patent: 2008/0191736 (2008-08-01), Redgrave et al.
patent: 2008/0222465 (2008-09-01), Redgrave et al.
patent: 2008/0258761 (2008-10-01), Hutchings et al.
patent: PCT/US2008/061072 (2008-04-01), None
Claims of Related Applications, Document listing claims of Related U.S. Appl. Nos. 11/375,562, 11/375,362, 11/375,363, 11/375,370, 11/375,364, and 11/375,561.
Non-final office action for U.S. Appl. No. 11/375,362, Jul. 18, 2007 (mailing date), Redgrave, Non-Final Office Action mailed Jul. 18, 2007 of Related Application.
Non-final office action for U.S. Appl. No. 11/375,363, Jul. 26, 2007 (mailing date), Redgrave, Non-Final Office Action mailed Jul. 26, 2007 of Related Application.
Non-final office action for U.S. Appl. No. 11/375,364, Jul. 6, 2007 (mailing date), Hutchings, Non-Final Office Action mailed Jul. 6, 2007 of Related Application.
Altera Corp., “Section V. In-System Design Debugging,”Quartus II Handbood,May 2007, pp. 1-150.
Amerson, R., et al., “Teramac—Configurable Custom Computing,”Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines,Apr. 19-21, 1995, pp. 32-38.
Arnold, J., “The Splash 2 Software Environment,”IDA Supercomputing Research Center,1993 Month N/A, pp. 88-93, Bowie, MD, USA.
Arnold, J., et al., “Splash 2,”Supercomputing Research Center,1992 Month N/A, pp. 316-322, Bowie, MD, USA.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference,May 1995, pp. 487-494.
Comptom, K., et al., “Reconfigurable Computing: A Survey of Systems and Software,”ACM Computing Surveys,Jun. 2002, pp. 171-210, vol. 34., No. 2.
Graham, P., “Logical Hardware Debuggers For FPGA-Based Systems,”A Dissertation Submitted to the Faculty of Brigham Young University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Brigham Young University,Dec. 2001, pp. i-246.
Hanono, S., “InnerView Hardware Debugger: A Logic Analysis Tool for the Virtual Wires Emulation System”,Submitted to the Department of Electrical Engineering and Computer science in Partial Fulfillment of the Requirements for the Degree of Master of Science at the Massachusetts Institute of Technology,Feb. 1995, pp. 1-59.
Hutchings, B., et al., “A CAD Suite for High-Performance FPGA Design,”Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines Defense Advanced Research Projects Agency,1999 Month N/A, pp. 1-16.
Hutchings, B., et al., “Designing and Debugging Custom Computing Applications,”IEEE Design&Test of Computers,Jan. 2000, pp. 20-28.
Hutchings, B., et al., “Unifying Simulation and Execution in a Design Environment for FPGA Systems,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems,Feb. 2001, pp. 201-205, vol. 9, No. 1.
Vuillemin, J., et al., “Programmable Active Memories: Reconfigurable Systems Come of Age,”Very Large Scale Integration(VLSI)Systems, IEEE Transactoinson vol. 4, Issue 1, Mar. 1996, pp. 56-69.
Xilinx, Inc., “ChipScope ProSoftware and Cores User Guide,” Jan. 10, 2007, pp. 1-206, Xilinx Inc.
Xilinx, Inc., “Virtex-5 FPGA,” Configuration User Guide, Feb. 2007, pp. 1-154, Xilinx, Inc.
Claims of Related Applications as of Jan. 20, 2008, Claims of Related Application with USPTO U.S. Appl. Nos. 11/375,562, 11/375,362, 11/375,363, 11/375,370, 11/375,364, and 11/375,561. The above-mentioned related applications (1) were listed as related applications in the Notice of Related Cases dated Sep. 16, 2006 and (2) have the same specification and drawing as the present application.
Trimberger, S., “Effects of FPGA Architecture on FPGA Routing,”32ndACM/IEEE Design Automation Conference,Jun. 1995, ACM.
Hauser, John R., “Garp: A MIPS Processor with a Reconfigurable Coprocessor”,FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on FPGA-Based Custom Computing Machines, Apr. 16-18, 1997, pp. 12-21.
Luk, Wayne, et al., “Compilation Tools for Run-Time Reconfigurable Designs”,FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on FPGA-Based Custom Computing Machines, Apr. 16-18, 1997, pp. 56-65.
Scalera, Stephen, et al., “The Design and Implementation of a Context Switching FPGA”,FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines, Apr. 15-17, 1998, pp. 78-85.
Non-Final Office Action of U.S. Appl. No. 12/050,897, Sep. 18, 2008 (mailing date), Redgrave, Jason, et al., Non-Final Office Action of commonly owned U.S. Appl. No. 12/050,897, listed as item #6 above.
Restriction Requirement of U.S. Appl. No. 11/375,363, Feb. 25, 2008 (mailing date), Redgrave, Jason, et al., Restriction Requirement of commonly owned U.S. Appl. No. 11/375,363, listed as item #8 above.
U.S. Appl. No. 12/235,581, Sep. 22, 2008 (filing date), Redgrave, Jason, et al., Commonly owned U.S. Appl. No. 12/235,581 with similar specification and drawings.
Notice of Allowance of U.S. Appl. No. 11/375,364, Aug. 27, 2008 (mailing date), Hutchings
Hutchings Brad
Khubchandani Teju
Redgrave Jason
Adeli & Tollen LLP
Tabula Inc.
Tran Anh Q
LandOfFree
Configurable IC with trace buffer and/or logic analyzer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Configurable IC with trace buffer and/or logic analyzer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable IC with trace buffer and/or logic analyzer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4076691