Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2007-12-18
2007-12-18
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S040000
Reexamination Certificate
active
11082199
ABSTRACT:
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of the sets are user multiplexers. Each particular user multiplexer has input and output terminals and has a set of select terminals for receiving a set of user-design signals that directs the particular multiplexer to connect a set of the input terminals to a set of the output terminals. The user-design signals are signals generated internally by the IC.
REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5369622 (1994-11-01), McLaury
patent: 5426378 (1995-06-01), Ong
patent: 5521835 (1996-05-01), Trimberger
patent: 5532958 (1996-07-01), Jiang et al.
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5768178 (1998-06-01), McLaury
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 5982655 (1999-11-01), Doyle
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6134154 (2000-10-01), Iwaki et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6163168 (2000-12-01), Nguyen et al.
patent: 6173379 (2001-01-01), Poplingher et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6205076 (2001-03-01), Wakayama
patent: 6233191 (2001-05-01), Gould et al.
patent: 6275064 (2001-08-01), Agrawal et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6346824 (2002-02-01), New
patent: 6348813 (2002-02-01), Agrawal et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6469540 (2002-10-01), Nakaya
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6496918 (2002-12-01), Dehon et al.
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6732068 (2004-05-01), Sample et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6809979 (2004-10-01), Tang
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6924663 (2005-08-01), Masui et al.
patent: 6937535 (2005-08-01), Ahn et al.
patent: 6956399 (2005-10-01), Bauer
patent: 6992505 (2006-01-01), Zhou
patent: 6998872 (2006-02-01), Chirania et al.
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7075333 (2006-07-01), Chaudhary et al.
patent: 7126372 (2006-10-01), Vadi et al.
patent: 7126856 (2006-10-01), Sun et al.
patent: 7129746 (2006-10-01), Balasubramanian et al.
patent: 7135886 (2006-11-01), Schlacter
patent: 2001/0007428 (2001-07-01), Young et al.
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0113619 (2002-08-01), Wong
patent: 2002/0125910 (2002-09-01), New et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0161568 (2002-10-01), Sample et al.
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0010767 (2004-01-01), Agrawal et al.
patent: 2004/0103265 (2004-05-01), Smith
patent: 2004/0196066 (2004-10-01), Ting
patent: 2004/0233758 (2004-11-01), Kim et al.
patent: 2005/0146352 (2005-07-01), Madurawe
U.S. Appl. No. 11/082,221, filed Mar. 15, 2005, Hutchings, Related Application.
U.S. Appl. No. 11/081,883, filed Mar. 15, 2005, Hutchings, Related Application.
U.S. Appl. No. 11/269,141, filed Nov. 7, 2005, Caldwell, Related Application.
U.S. Appl. No. 11/081,850, filed Mar. 15, 2005, Hutchings, Related Application.
U.S. Appl. No. 11/269,168, filed Nov. 7, 2005, Redgrave, Related Application.
“§3 Programmable Logic Devices,”Digital System Design, 2001, pp. 3.1-3.28, no month.
“Design for Low Power in Actel Antifuse FPGAs”, Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8.
“The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, pp. 1-10, no date.
“The Xilinx Virtex Series FPGA,” Jan. 22, 2001, slides 1-22.
“Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,”ISCA'04, 2004, ACM, Munchen, Oberbayem, Germany, no month.
Agrawal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions,”FPGA 99, 1999, pp. 17-26, ACM, Monterey, CA, USA, no month.
Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,”FPGA 2000, 2000, ACM, Monterey, CA, USA, no month.
Altera Corp., “6. DSP Blocks in Stratix II Devices,”SII52006-1.0, Feb. 2004, pp. 1-32.
Altera, “Stratix II DSP Performance,”White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, CA.
Backus, J., “Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs,”Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM.
Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set,”A Technology Application Whitepaper, 2004, pp. 1-8, QuickSilver A Technology, Inc., San Jose, California, no month.
Brand, D., et al., “Minimaization of AND-EXOR Expressions Using Rewrite Rules,”IEEE Transactions on Computers, May 1993, pp. 568-576, IEEE.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, 1995, pp. 487-494, IEEE, no month.
Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” 2003, pp. 1-74, Synopsys, Inc., no month.
Caspi, E., et al., “A Streaming Multi-Threaded Model,”MSP-3, Dec. 2, 2001, pp. 1-23.
Caspi, E., et al., “Stream Computations Organized for Reconfigurable Executiion (SCORE): Introduction and Tutorial,” Aug. 25, 2000, pp. 1-31, Version 1.0.
Ciemat, J.V., et al., “Annealing
Hutchings Brad
Schmit Herman
Teig Steven
Adeli Law Group PLC
Tabula Inc.
Tan Vibol
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