Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-03-30
2002-08-20
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S036000, C710S038000, C710S100000, C710S107000
Reexamination Certificate
active
06438624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic data communications and integrated circuits (ICs), and more particularly to a method of configuring input/output (I/O) expander addresses on a communications bus, to facilitate inter-IC communications among a plurality of I/O planars used in a computer system.
2. Description of Related Art
Modern electronic circuits use many different types of logic components (e.g., processing units and microcontrollers) to carry out numerous functions. These circuits require a multitude of conductive pathways, or buses, to provide communications or connectivity between the logic components. A communications bus (transmission line) may be used to transmit certain values, such as data (operands) which are input to a logic component, or instructions used by the logic components, and further may be used to transmit various control signals. Buses can be unidirectional, bidirectional, or broadcast (used to interconnect three or more devices and allow simultaneous or sequential access to information or controls conveyed on the bus). These buses may be external, e.g., laid out on a printed circuit board, and interconnecting two or more devices which are separately packaged. They may also be internal, interconnecting two or more devices which are fabricated in a single package, such as an integrated circuit (IC).
Buses are used to interconnect devices for a wide variety of applications, including communications between complex computer components such as microprocessors, application specific integrated circuits (ASICs), peripheral devices, random-access memory, etc. Several different external bus designs have been developed for interconnecting various computer components. Early designs include the “expansion” bus referred to as the XT bus, and the later AT bus, also referred to as the Industry Standard Architecture (ISA) bus. A 32-bit extension to this bus was later created, which is referred to as the Extended Industry Standard Architecture (EISA). Another well-known external bus design is the Peripheral Component Interconnect (PCI) bus.
FIG. 1
illustrates a conventional computer system
10
using some of the foregoing buses. Computer system
10
has several processing units (CPUs)
12
a
,
12
b
, and
12
c
which are connected, via a system bus
14
, to a system memory device
16
(random-access memory or RAM) that is used by the processing units to carry out program instructions, and firmware
18
whose primary purpose is to seek out and load an operating system from a peripheral device (usually the permanent memory device or hard disk) whenever the computer is first turned on. The processing units are connected to various peripheral devices via a PCI host bridge
20
. These peripheral devices comprise PCI devices
22
and
24
connected to the PCI bus
26
, and an ISA device
28
connected to an ISA bus
30
which is connected to an ISA bridge
32
. These input/output (I/O) devices may include, for example, a display monitor, keyboard, graphical pointer device (mouse), a permanent storage device (direct access storage device or DASD), etc.
Another widely recognized bus design used for microelectronics is known as the I
2
C bus. The term “I
2
C” is an abbreviation for “inter-IC,” referring to communications between two or more integrated circuits. The bus physically consists of two active wires and a ground connection. The active wires (data and clock) are both bidirectional. An exemplary configuration using an I
2
C bus is shown in FIG.
2
. Two microcontrollers
34
and
36
are connected to the clock and data lines, along with various other circuits such as a liquid crystal display (LCD) driver
38
, a memory unit
40
, and a data converter
42
.
The I
2
C protocol supports multiple “masters,” meaning that multiple chips can be interconnected to the same bus and each one can act as a master. The IC that initiates a given data transfer on the bus is considered the bus master. For that data transfer, all the other devices are regarded as “slaves.” Every component connected to the bus has its own unique address, which is used to indicate a target for data. Each of these chips can act as a receiver or transmitter depending on its intended functionality.
The I
2
C bus design is used in many microcontroller-based applications for control, diagnostics or power management, and is especially useful in video devices such as computer monitors, televisions and VCRs. This design was originally created to provide an easy way to connect a CPU to peripheral chips in a television set, and is still commonly used to connect computer systems to peripheral devices. For example, some versions of the PowerPC™ processor sold by International Business Machines Corp. (IBM—assignee of the present invention) are provided with an I
2
C port to offer an alternative communications path for selected peripherals. IBM's Netfinity™ rack server system uses such a service processor to allow I
2
C communications with I/O subsystems. The service processor communicates with all I/O planars using the I
2
C bus to access information like vital product data (VPD) codes, planar voltages, temperatures, etc. The I/O planars are located in the rack on a base I/O drawer and one or more expansion I/O drawers.
I/O planars can use an I/O expander to select one of several I
2
C channels of the I/O subsystem. One example is the PCF8574 remote 8-bit I/O expander. The PCF8574 is a complementary metal-oxide semiconducting (CMOS) circuit that provides general purpose remote I/O expansion for most microcontroller families via an I
2
C bus. The device has an interrupt line which can be directly connected to the interrupt logic of a microcontroller. By sending an interrupt signal on this line, the remote I/O planar can inform the microcontroller if there is incoming data on its ports without having to communicate via the I
2
C bus, so the PCF8574 can remain a simple slave device.
One problem that has arisen in such uses of I
2
C systems, is the limitation imposed by the addressing scheme required as part of the I
2
C protocol. All I/O planars (in both the base I/O drawer and expansion I/O drawer) have the same I
2
C design, meaning that the I/O expander of each planar will have the same address when the system is first powered on. Accordingly, it is necessary to configure the I
2
C I/O expander addresses of all I/O planars, to different addresses. In the prior art, this configuration is performed manually, such as by using jumpers to interconnect address pins on the expanders, or using cables attached to the drawer frame providing an individual address. These approaches, requiring human involvement, easily result in errors, and require additional hardware. It would, therefore, be desirable to devise an improved method of addressing I
2
C components that allows a large number of devices to be easily interconnected to the I
2
C bus. It would be further advantageous if the method automatically provided appropriate addressing without requiring extra hardware.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide improved communications between logic components such as processors, microcontrollers and input/output (I/O) devices.
It is another object of the present invention to provide a method for achieving such improved communications which is applicable to an I
2
C bus and devices such as an I/O expander.
It is yet another object of the present invention to provide an improved method of addressing logical devices which are interconnected using a communications bus.
The foregoing objects are achieved in a method of configuring a data communications system, generally comprising the steps of connecting a first logic component to a first communications bus, connecting a second logic component to the first communications bus wherein the second logic component has a default communications address, connecting a third logic component to a second communications bus, changing the default communications address of the se
Ku Yi-Ming
Tuten Wallace
Dillon Andrew
Gaffin Jeffrey
International Business Machines - Corporation
Perveen Rehana
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