Configurable high-speed memory interface subsystem

Details Configurable high-speed memory interface subsystem Configurable high-speed memory interface subsystem

2005-08-05

2008-10-14

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S004000, C711S100000, C711S106000, C711S111000, C365S189011, C365S189011, C365S189020, C365S189030, C365S189040, C365S189050, C365S189140, C365S189150, C365S189160, C365S189170, C365S189180, C365S191000, C365S193000, C365S194000, C365S195000, C365S223000, C365S233110, C365S233130

Reexamination Certificate

active

07437500

ABSTRACT:
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

REFERENCES:
patent: 6601126 (2003-07-01), Zaidi et al.
patent: 7132866 (2006-11-01), Jiang
patent: 7177208 (2007-02-01), Smith et al.
patent: 2004/0117566 (2004-06-01), McClannahan et al.
patent: 2006/0023698 (2006-02-01), Shore et al.

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