Configurable high-speed memory interface subsystem

Details Configurable high-speed memory interface subsystem Configurable high-speed memory interface subsystem

2011-01-04

2011-01-04

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S004000, C711S100000, C711S111000, C711S106000, C365S189180, C365S189020, C365S189030, C365S189040, C365S189050, C365S189140, C365S189150, C365S189160, C365S189170, C365S191000, C365S192000, C365S193000, C365S194000, C365S195000, C365S233110, C365S233130

Reexamination Certificate

active

07865661

ABSTRACT:
A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

REFERENCES:
patent: 6601126 (2003-07-01), Zaidi et al.
patent: 7132866 (2006-11-01), Jiang
patent: 7177208 (2007-02-01), Smith et al.
patent: 7437500 (2008-10-01), Butt et al.
patent: 2004/0117566 (2004-06-01), McClannahan et al.
patent: 2006/0023698 (2006-02-01), Shore et al.

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