Configurable emphasis for high-speed transmitter driver...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

Reexamination Certificate

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Details

C326S087000

Reexamination Certificate

active

07924046

ABSTRACT:
Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Otherwise the output signal for said one bit is based on the first current without regard for the second current. The second mode may be similar to the first mode when said one bit has the same value as the immediately preceding bit; but otherwise the output signal for said one bit is based on the first current increased by the second current. As an alternative to using the immediately preceding bit (as in the above “post-tap” operation), the immediately succeeding (following) bit may be used in generally the same way (in so-called “pre-tap” operation).

REFERENCES:
patent: 7557615 (2009-07-01), Tran et al.
patent: 7583753 (2009-09-01), Okamura
patent: 2004/0124888 (2004-07-01), Radelinow
patent: 2006/0006901 (2006-01-01), Groen et al.

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