Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-08-16
2002-08-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000, C326S044000, C326S095000, C326S098000
Reexamination Certificate
active
06433581
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to dynamic programmable logic arrays (DPLAs) and specifically to a DPLA that is configurable.
BACKGROUND OF THE INVENTION
A PLA (programmable logic array) produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs, implemented using an AND plane to generate the product terms and an OR plane to generate the sums of the product terms. A dynamic PLA implements the sum-of-products functions by precharging and conditionally discharging wired-NOR circuits that are built within the AND and OR arrays. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built.
Dynamic programmable logic arrays (DPLAs) are utilized extensively. As shown in
FIG. 1
, a DPLA
5
includes input signals
2
to an AND plane
10
whose outputs
18
are then the inputs to an OR plane
14
that produces the output signals
20
. The outputs of the AND plane
10
are known as AND term signals (A
1
to Am). The outputs of the OR plane are known as OR term signals (O
1
to On).
FIG. 1
shows k number of inputs, m number of AND term signals, and n number of OR term signals. The AND plane
10
further comprises multiple NOR term generators
12
, each of which outputs a wired-NOR signal
18
that is first precharged to Vcc (the supply voltage) and then conditionally discharged to GND (the ground voltage). The Vcc and GND can represent high (TRUE) and low (FALSE) logic states, respectively. Similarly, the OR plane
14
also comprises multiple NOR term generators
16
, each of which outputs a wired-NOR signal
20
that is first charged to high logic level and then conditionally discharged to low logic level. For simplicity, the clocks that control the precharge and discharge are not shown in FIG.
1
.
FIG. 2
shows two NOR term generators
12
in the AND plane. The wired-NOR signal
30
is discharged if one or more input signals
2
that are “programmed” to affect this output signal are high. An input signal
2
is programmed to affect an output signal by providing an evaluate circuitry
32
controlled by the input signal
2
.
FIG. 2
shows that the input signals I
1
and I
2
are programmed to affect the AND term signals A
1
and A
2
. If the evaluate circuitry labeled
34
were not provided, for example, then the input signal I
1
cannot affect the AND term signal A
1
while it still affects the AND term signal A
2
.
FIG. 3
shows a conventional evaluate circuitry
38
for DPLA and the precharge transistor
40
and the discharge transistor
42
for the AND term signal. This precharge and conditional discharge circuitry is controlled in two non-overlapping phases, known as precharge and evaluate. During the precharge phase, both CLKP and CLKD are held low so that precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, both CLKP and CLKD are held high so that the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if the input signal
46
is high to turn on the evaluate transistor
44
, then the charge stored at the output signal NL is discharged via the transistors
44
and
42
, resulting in the signal NL being low. If on the other hand, if the input signal
46
is low during the evaluate phase, the evaluate transistor
44
is turned off and the charge stored at the output signal NL remains high. The input signal
46
must not change during the evaluate phase to avoid falsely discharging the output signal NL.
A NOR term generator
12
, which comprises one precharge transistor and one discharge transistor and at least one evaluate circuitry, works as follows. During the precharge phase, the precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if one or more input signals that are programmed to affect this output are high, the charge stored at the output signal NL is discharged and NL becomes low. If none of the input signals are high, then there is no path for the charge stored at NL to be discharged and the NL remains high. The NOR term generators
16
in the OR plane
14
works as same as those in the AND plane
10
.
A detailed description of DPLA can be found in “Principles of C-MOS VLSI Design” by N. H. Weste and K. Eshraghian, Addison-Wesley, 2
nd
Edition, 1993, Chapter 8, pages 592-602 or in the U.S. Pat. No. 4,769,562.
Accordingly, a DPLA produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs. The DPLA implements the sum-of-products functions by precharging and discharging wired-NOR circuits that are built within the array. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built. Therefore, if a different function is desired the DPLA is inflexible and must be replaced after being programmed.
Accordingly, what is needed is a system and method for allowing a DPLA to be configurable. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A configurable dynamic PLA in accordance with the present invention provides for multiple programs onto one dynamic PLA and allows one of the multiple programs to be selected at any given time, making the array “configurable” after the array is built. In addition, if the evaluate module are made reprogrammable, the PLA is both configurable and reprogrammable.
The capability to reprogram the array allows new functions to be realized after the array is built. The capability to configure the array allows any one of the preprogrammed functions—be it hardwired or reprogrammed—to be selected for each evaluation cycle. This is especially useful, since reprogramming the array may take multiple cycles.
REFERENCES:
patent: 4769562 (1988-09-01), Ghisio
patent: 4950928 (1990-08-01), Schnizlein
patent: 5926038 (1999-07-01), Fouts et al.
patent: 6023179 (2000-02-01), Klass
patent: 6075385 (2000-06-01), Dorweiler et al.
patent: 6229338 (2001-08-01), Coulman et al.
Elan Research
Sawyer Law Group LLP
Tan Vibol
Tokar Michael
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