Configurable delay chain with stacked inverter delay elements

Details Configurable delay chain with stacked inverter delay elements Configurable delay chain with stacked inverter delay elements

2007-12-18

2007-12-18

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S119000, C326S122000, C327S276000

Reexamination Certificate

active

11020746

ABSTRACT:
A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

REFERENCES:
patent: 4498021 (1985-02-01), Uya
patent: 5166555 (1992-11-01), Kano
patent: 5414312 (1995-05-01), Wong
patent: 5455521 (1995-10-01), Dobbelaere
patent: 5497105 (1996-03-01), Oh et al.
patent: 5698994 (1997-12-01), Tsuji
patent: 5767700 (1998-06-01), Lee
patent: 5791715 (1998-08-01), Nebel
patent: 5963074 (1999-10-01), Arkin
patent: 5969543 (1999-10-01), Erickson et al.
patent: 6025738 (2000-02-01), Masleid
patent: 6114840 (2000-09-01), Farrell et al.
patent: 6172545 (2001-01-01), Ishii
patent: 6262601 (2001-07-01), Choe et al.
patent: 6321282 (2001-11-01), Horowitz et al.
patent: 6573777 (2003-06-01), Saint-Laurent et al.
patent: 6577176 (2003-06-01), Masleid et al.
patent: 6731140 (2004-05-01), Masleid et al.
patent: 2001/0000426 (2001-04-01), Sung et al.
patent: 2001/0030561 (2001-11-01), Asano et al.
patent: 2002/0056016 (2002-05-01), Horowitz et al.
patent: 2003/0042960 (2003-03-01), Gomm
patent: 2003/0057775 (2003-03-01), Yamashita et al.
patent: 2003/0160630 (2003-08-01), Earle
patent: 2003/0231713 (2003-12-01), Masleid et al.
patent: 2004/0124900 (2004-07-01), Brox
patent: 03089624 (1991-04-01), None
Nalamalpu et al., “Boosters for Driving Long Onchip Interconnects- Design Issues, Interconnect Synthesis, and Comparison with Repeaters”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 1, Jan. 2002.

Affiliated with

Also associated with

Rating

Configurable delay chain with stacked inverter delay elements does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Configurable delay chain with stacked inverter delay elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configurable delay chain with stacked inverter delay elements will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3895622