Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-03-02
2004-03-16
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S039000, C714S726000, C703S028000, C717S124000
Reexamination Certificate
active
06708290
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to software and hardware testing environments, and more particularly to software and hardware testing tools for debugging systems that include one or more processing units or microprocessors.
BACKGROUND OF THE INVENTION
As advances are made in the technology for manufacturing integrated circuits, the capability and complexity of hardware and software for embedded systems increases. This continual increase in capability and complexity brings a continuing challenge for the software development tools used to create and debug applications for embedded hardware.
Embedded systems developers are facing a problem of “vanishing visibility”. It is increasingly harder to see in real time what's happening within an application, due to higher processor speeds, higher integration levels, and larger on-chip caches. “System-on-a-chip” solutions are incorporating more and more ASIC peripherals. Capabilities that used to be off-chip, and easily accessible for monitoring with logic analyzers, are now on-chip. The more traditional solutions of using logic analyzers and in-circuit emulators are quickly becoming insufficient to support the debugging needs of today's developers.
In recent years, a partial solution to this problem has been introduced. JTAG emulation has replaced in-circuit emulation. A JTAG test port is integrated into the microprocessor permitting data to be moved on-and off-chip without interrupting the executing device. And, in some microprocessors, this capability is augmented with additional emulation logic to provide even greater visibility and access into registers and other internal functions such as on-chip cache memories.
Some software tools have been created to aid the developer in using this enhanced debugging capability but they have tended to be rather primitive. These tools are usually designed to work with only one hardware design and must be partially to completely rewritten each time a new design is introduced. Given the pace of technology change, modifying software debug tools or creating new ones for each new hardware innovation in embedded systems is prohibitively expensive. As such, these system have a hardware centric view.
In addition, these software tools tend to be limited in their capabilities and in their ease-of-use. They have generally been created by hardware designers who think in terms of registers, comparators, addresses, etc. instead of in terms of the tasks or jobs the developer wishes to accomplish. In other words, the tools are hardware-centric rather than user-centric. The software developer has to be familiar with how the hardware works to accomplish even simple tasks such as setting a breakpoint.
Finally, the “system-on-a-chip” solutions are introducing a new problem for the developers and users of the software debug tools targets for these solutions. Hardware designs are no longer limited to a few, set configurations. Hardware designers can vary the capabilities of their “system-on-a-chip” to meet the needs of the target application. Therefore, to avoid requiring the software developers to learn a new hardware architecture and a new set of debug tools each time, the debug tools need to adapt themselves to the capabilities of the hardware.
SUMMARY OF THE INVENTION
An illustrative embodiment of the present invention seeks to provide a software system and method for automatically determining capabilities of a hardware system to permit a software development system to support multiple hardware system architectures. In this method, a database is accessed that corresponds to the hardware system to be used during a software debug system. This hardware system is selected from multiple possible hardware system architectures. Then, a software representation of the set of debug components available on the selected hardware system is created in accordance with the database description of the hardware system. This software representation, which will be used by the software development system as debug jobs are specified, contains a representation of each component and of the interconnections between the components. The software development system then accepts a request for a debug job. This request is comprised of at least one action and one or more events that will trigger the action. The software representation is traversed to determine if debug components are available to fulfill the debug job request. Finally, the requested debug job is performed using a set of debug components that was selected when the software representation was traversed.
In one embodiment of the invention, the step of creating a software representation includes creating a software object that corresponds exactly to one debug component. In this manner, every debug component on the hardware system is represented by exactly one software object. In addition, linkage information is provided in each of the objects to represent how the debug components are interconnected in the hardware system, thus creating a software “wire list”.
In another embodiment of the invention, the step of traversing the software representations includes the steps described herein. The software representation of the debug components is queried to determine if any of the components can perform a requested action. If a component is identified, the linkage information is followed to identify the set of interconnected debug components. This set of interconnected components is then queried to determine if these components are capable of detecting one or more events in such a manner that the action will be triggered when the event or events occur.
In another embodiment of the invention, the step of traversing the software representation includes identifying the lowest cost set of components that can accomplish the requested task.
These and other features of the invention that will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
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Baderman Scott
Brady III W. James
Marshall, Jr. Robert D.
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