Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-06-16
2001-09-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06294927
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to application-specific integrated circuits generally and more particularly to the structure of the principal building blocks of gate arrays in multi-metal semiconductor devices.
BACKGROUND OF THE INVENTION
Application specific integrated circuits (ASICs) are microelectronic devices that are designed and configured to carry out sets of instructions for specific applications. Application specific integrated circuits are preferable over general-purpose of-the-shelf devices when speed, performance or device compactness is desired, or when the specific functionality cannot be obtained by available devices. Generally, the logic portion of an ASIC device is implemented by either standard cell or gate array technology. In the gate array technology an array of cells comprising simply interconnected transistors is provided by tiling and repeating the same cell over and over again. Sometimes a gate array block may be found within a standard cell device or a full custom device. In gate array technology, the metal interconnections are customized for each application. The customization of the metal interconnection layers determines the functionality of the cells and enables the desired application.
For purpose of simplicity, cost savings and short delivery time it is desirable to minimize the number of metal interconnect layers that need to be modified to implement a given functionality. For that purpose, the repetitive cells that build the array must be designed and constructed so they can provide simple as well as complex functionality with minimal overall modifications of the device.
U.S. Pat. Nos. 5,684,412, 5,751,165 and 5,861,641 describe logic cells comprising a cascade of multiplexers that are useful for a gate array that can be programmer by modifying only one or two layers of a multi-layer interconnect structure of the device. The function of each of these cells is input selectable. However, those logic cell structures have the drawback that when it is desirous to implement two simple functions such as two inverters in parallel, two separate unit logic cells have to be employed. This reduces the area utilization of the device, reduces its performance and increases its cost.
The following additional U.S. Patents also represent the state of the prior art: U.S. Pat. Nos. 5,751,162; 5,428,304.
SUMMARY OF THE INVENTION
The present invention seeks to provide an improved customizable logic array device and cell therefor.
There is thus provided in accordance with a preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including at least first and second multiplexers, each having a select input and an output, at least two inverters, each having an input and an output, and electrical connections, selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the input of one of the at least two inverters.
Further in accordance with a preferred embodiment of the present invention the at least first and second multiplexers include at least three multiplexers and the at least two inverters include at least three inverters.
Still further in accordance with a preferred embodiment of the present invention the multiplexers are implemented in at least one metal layer and said electrical connections include vias connecting said at least one metal layer to another metal layer other than said at least one metal layer.
Preferably the another metal layer is a top metal layer.
Alternatively, the another metal layer is an intermediate metal layer.
Moreover in accordance with a preferred embodiment of the present invention the another metal layer is a metal layer lying immediately above the at least one metal layer.
Additionally in accordance with a preferred embodiment of the present invention the cell being further characterized in that it has a programmable logic function. Preferably the programmable logic function is programmable by selection of at least one input to the at least first and second multiplexer and by selectable connection of the electrical connections.
Additionally, the selectable connection is effected by metal deposition patterned and etched.
Alternatively, the selectable connection is effected by application of laser energy to the electrical connections for eliminating portions thereof.
Still further in accordance with a preferred embodiment of the invention the selectable connection may be effected by application of electrical energy to the electrical connections.
Additionally in accordance with a preferred embodiment of the present invention the selectable connection is effected by metal deposition and etching.
Further in accordance with a preferred embodiment of the present invention the cell includes at least three inverters each having generally identical driving power.
Still further in accordance with a preferred embodiment of the present invention at least two of the at least three inverters each have generally identical driving power and a third of the at least three inverters has a driving power different from the driving power of the at least two of the at least three inverters.
Furthermore in accordance with a preferred embodiment of the present invention at least two of the at least three inverters each have generally identical driving power and a third of the at least three inverters has a driving power which is at least double the driving power of each of the at least two of the at least three inverters.
Furthermore in accordance with a preferred embodiment of the present invention the cell includes no more than three multiplexers, no more than five inverters and only a single NAND gate.
There is also provided in accordance with yet another preferred embodiment of the present invention a cell forming part of a customizable logic array device, the cell including at least first and second multiplexers, at least two inverters, and electrical connections, selectably connecting the at least first and second multiplexers and the at least two inverters such that the multiplexers operate either in parallel or in series.
Further in accordance with a preferred embodiment of the present invention the multiplexers are implemented in at least one metal layer and the electrical connections include vias connecting the at least one metal layer to another metal layer other than the at least one metal layer.
Preferably the another metal layer is a top metal layer.
Alternatively, the another metal layer is an intermediate metal layer.
Moreover in accordance with a preferred embodiment of the present invention the another metal layer is a metal layer lying immediately above the at least one metal layer.
There is also provided in accordance with another preferred embodiment of the present invention a customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers, each having a select input and an output, at least two inverters, each having an input and an output, and electrical connections, selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the input of one of the at least two inverters.
Further in accordance with a preferred embodiment of the present invention the at least first and second multiplexers include at least three multiplexers and the at least two inverters include at least three inverters.
There is further provided in accordance with yet another preferred embodiment of the present invention a customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers, at least two inverters, and electrical connections, selectably connecting the at least first and second multiplexers and the at least two inverters such that the multiplexers operate either in parallel or in series.
REFERENCES:
patent: 5428304 (1995-06-01), Landers et al.
patent: 5684412 (1997-11-01), Yoeli et al.
patent: 5751162 (1998-05-01), Mehendale et al.
patent: 5751165 (1
Janai Meir
Yoeli Uzi
Chip Express (Israel) LTD
Ladas & Parry
Le Don Phu
Tokar Michael
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