Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2011-01-25
2011-01-25
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S154000, C711S212000
Reexamination Certificate
active
07877537
ABSTRACT:
A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.
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Lahti Gregg D.
Pesavento Rodney J.
Triece Joseph W.
King & Spalding L.L.P.
Lane Jack A
Microchip Technology Incorporated
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