Configurable cache allowing cache-type and buffer-type access

Details Configurable cache allowing cache-type and buffer-type access Configurable cache allowing cache-type and buffer-type access

2007-02-27

2007-02-27

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S205000, C711S118000, C711S170000

Reissue Patent

active

10901482

ABSTRACT:
A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

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