Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2006-11-07
2006-11-07
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S118000, C711S130000
Reexamination Certificate
active
07133997
ABSTRACT:
A method, apparatus, and system for configuring an address bit in a cache formed on an integrated circuit. The method, apparatus, and system include the ability to configure the address bit as either a tag bit or a set index bit and reconfigure the address bit.
REFERENCES:
patent: 4503501 (1985-03-01), Coulson et al.
patent: 4788656 (1988-11-01), Sternberger
patent: 5367653 (1994-11-01), Coyle et al.
Buckley Maschoff & Talwalkar LLC
Intel Corporation
Nguyen T
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