Configurable architecture hybrid analog/digital delay locked...

Details Configurable architecture hybrid analog/digital delay locked... Configurable architecture hybrid analog/digital delay locked...

2011-01-25

2011-01-25

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

07876137

ABSTRACT:
A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.

REFERENCES:
patent: 6628154 (2003-09-01), Fiscus
patent: 2004/0125905 (2004-07-01), Vlasenko et al.
patent: 2008/0157836 (2008-07-01), Cho

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