Configurable advanced technology attachment/integrated drive...

Details Configurable advanced technology attachment/integrated drive... Configurable advanced technology attachment/integrated drive...

2007-09-25

2007-09-25

Sparks, Donald (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S300000, C710S305000, C710S008000

Reexamination Certificate

active

10846739

ABSTRACT:
An ATA/IDE host controller100generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers121. An internal timing control module110provides either the default timing parameters or the override timing parameters to the IDE host interface102, according to the programmable override control301.

REFERENCES:
patent: 4893271 (1990-01-01), Davis et al.
patent: 5394541 (1995-02-01), Chesley et al.
patent: 5579025 (1996-11-01), Itoh
patent: 6779062 (2004-08-01), Eschmann et al.
patent: 2003/0149906 (2003-08-01), Wang
patent: 2004/0030821 (2004-02-01), Qiu

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